Semiconductor device
A semiconductor device includes: a substrate including a cell array area, a periphery circuit area, and an interface area; bit lines arranged in the cell array area and extending in a first horizontal direction; a mold insulating layer arranged on the bit lines and including openings extending in a second horizontal direction; channel layers respectively arranged on the bit lines in each of the openings; word lines respectively arranged on the channel layers and extending in the second horizontal direction from the cell array area to the interface area, the word lines including a first word line on a first sidewall of each opening of the mold insulating layer and a second word line on a second sidewall of the opening; and a trimming insulating block arranged in the interface area and connected to an end of the first word line and an end of the second word line.
1 . A semiconductor device comprising:
a substrate including a cell array area, a periphery circuit area, and an interface area between the cell array area and the periphery circuit area;
a plurality of bit lines arranged in the cell array area of the substrate and extending in a first horizontal direction;
a mold insulating layer arranged on the plurality of bit lines, the mold insulating layer including a plurality of openings extending lengthwise in a second horizontal direction;
a plurality of channel layers respectively arranged on the plurality of bit lines in each of the plurality of openings of the mold insulating layer;
a plurality of word lines respectively arranged on the plurality of channel layers and extending lengthwise in the second horizontal direction from the cell array area to the interface area, the plurality of word lines including a first word line arranged on a first sidewall of each opening of the mold insulating layer and a second word line arranged on a second sidewall of the opening; and
a trimming insulating block arranged in the interface area of the substrate and connected to an end of the first word line and an end of the second word line.
2 . The semiconductor device of claim 1 , wherein the trimming insulating block extends in the first horizontal direction, and crosses both a first opening and a second opening of the plurality of openings adjacent to each other in the first horizontal direction.
3 . The semiconductor device of claim 2 , wherein the trimming insulating block contacts an end of each of the plurality of word lines.
4 . The semiconductor device of claim 1 ,
wherein the plurality of channel layers comprises:
a first vertical extension portion arranged on the first sidewall of the opening of the mold insulating layer;
a second vertical extension portion arranged on the second sidewall of the opening; and
a horizontal extension portion arranged on a bottom portion of the opening and arranged on the bit line,
wherein the first word line is arranged on a sidewall of the first vertical extension portion, and
wherein the second word line is arranged on a sidewall of the second vertical extension portion.
5 . The semiconductor device of claim 1 ,
wherein the first word line comprises:
a main extension portion arranged in the cell array area and extending in the second horizontal direction; and
a bending portion arranged in the interface area, connected to the main extension portion, and extending in the first horizontal direction,
wherein the main extension portion and the bending portion of the first word line contact the trimming insulating block,
wherein the second word line comprises a main extension portion arranged in the cell array area and extending in the second horizontal direction, and
wherein the main extension portion of the second word line contacts the trimming insulating block.
6 . The semiconductor device of claim 5 , further comprising a word line contact arranged in the interface area and arranged on the bending portion of the first word line.
7 . The semiconductor device of claim 1 ,
wherein the plurality of openings comprise a first opening and a second opening adjacent to each other in the first horizontal direction, and
wherein a first portion of the trimming insulating block vertically overlaps the first opening, and a second portion of the trimming insulating block vertically overlaps the second opening.
8 . The semiconductor device of claim 1 ,
wherein the plurality of openings comprise a first opening and a second opening adjacent to each other in the first horizontal direction, and
wherein the trimming insulating block comprises:
a first trimming insulating block vertically overlapping the first opening; and
a second trimming insulating block vertically overlapping the second opening and arranged apart from the first trimming insulating block.
9 . The semiconductor device of claim 1 ,
wherein an upper surface of the trimming insulating block is at a level higher than an upper surface of the plurality of word lines, and
wherein a bottom surface of the trimming insulating block is at a level equal to or lower than a bottom surface of the plurality of word lines.
10 . The semiconductor device of claim 1 ,
wherein the plurality of channel layers comprises:
a first vertical extension portion arranged on the first sidewall of the opening of the mold insulating layer;
a second vertical extension portion arranged on the second sidewall of the opening; and
a horizontal extension portion arranged on a bottom portion of the opening and arranged on the bit line, and
wherein each of the plurality of channel layers comprises a U-shaped vertical cross-section.
11 . The semiconductor device of claim 10 , further comprising:
in the cell array area, a landing pad arranged on each of the first vertical extension portion and the second vertical extension portion of the plurality of channel layers;
word line contacts arranged on end portions of the plurality of word lines in the interface area; and
a routing wiring line arranged on the word line contact in the interface area, and arranged at a same vertical level as the landing pad.
12 . The semiconductor device of claim 1 , further comprising:
a periphery circuit arranged in the cell array area, the periphery circuit arranged between the substrate and the plurality of bit lines, and electrically connected to the plurality of bit lines; and
a shielding structure extending between the plurality of bit lines in the first horizontal direction.
13 . A semiconductor device comprising:
a substrate including a cell array area, a periphery circuit area, and an interface area between the cell array area and the periphery circuit area;
a plurality of bit lines arranged in the cell array area of the substrate and extending in a first horizontal direction;
a plurality of channel layers respectively arranged on the plurality of bit lines, each of the plurality of channel layers including a first vertical extension portion and a second vertical extension portion spaced apart from each other in the first horizontal direction, and a horizontal extension portion connected to a bottom portion of the first vertical extension portion and a bottom portion of the second vertical extension portion;
a plurality of word lines respectively arranged on the plurality of channel layers and extending lengthwise from the cell array area to the interface area in a second horizontal direction, the plurality of word lines including a first word line arranged on a sidewall of the first vertical extension portion of the plurality of channel layers and a second word line arranged on a sidewall of the second vertical extension portion of the plurality of channel layers; and
a trimming insulating block arranged in the interface area of the substrate and connected to an end of the first word line and an end of the second word line.
14 . The semiconductor device of claim 13 , wherein the first word line comprises:
a main extension portion arranged in the cell array area and extending in the second horizontal direction; and
a bending portion arranged in the interface area, connected to the main extension portion, and extending in the first horizontal direction,
wherein the main extension portion and the bending portion of the first word line contact the trimming insulating block,
wherein the second word line comprises a main extension portion arranged in the cell array area and extending in the second horizontal direction, and
wherein the main extension portion of the second word line contacts the trimming insulating block.
15 . The semiconductor device of claim 14 , further comprising a word line contact arranged in the interface area and arranged on the bending portion of the first word line.
16 . The semiconductor device of claim 14 ,
wherein an upper surface of the trimming insulating block is at a level higher than an upper surface of the plurality of word lines, and
wherein a bottom surface of the trimming insulating block is at a level equal to or lower than a bottom surface of the plurality of word lines.
17 . The semiconductor device of claim 14 , further comprising:
a mold insulating layer arranged on the plurality of bit lines, the mold insulating layer including a plurality of openings extending in the second horizontal direction,
wherein the first word line is arranged on a first sidewall of each of the plurality of openings, and the second word line is arranged on a second sidewall of each of the plurality of openings.
18 . The semiconductor device of claim 17 ,
wherein the trimming insulating block extends in the first horizontal direction, and
wherein the trimming insulating block crosses at least two of the plurality of openings arranged in the first horizontal direction.
19 . The semiconductor device of claim 17 ,
wherein the trimming insulating block is formed in plural, and
wherein each of the trimming insulating blocks vertically overlaps one of the plurality of openings arranged in the first horizontal direction.
20 . A semiconductor device comprising:
a substrate including a cell array area, a periphery circuit area, and an interface area between the cell array area and the periphery circuit area;
a periphery circuit arranged in the cell array area of the substrate;
a plurality of bit lines arranged in the cell array area of the substrate and extending in a first horizontal direction;
a mold insulating layer arranged on the plurality of bit lines, the mold insulating layer including a plurality of openings extending in a second horizontal direction;
a plurality of channel layers respectively arranged on the plurality of bit lines in each of the plurality of openings of the mold insulating layer;
a plurality of word lines arranged on the plurality of channel layers and extending in the second horizontal direction from the cell array area to the interface area, the plurality of word lines including a first word line arranged on a first sidewall of each opening of the mold insulating layer and a second word line arranged on a second sidewall of the opening of the mold insulating layer;
a trimming insulating block arranged in the interface area of the substrate and connected to an end of the first word line and an end of the second word line;
landing pads respectively arranged on the plurality of channel layers in the cell array area;
word line contacts arranged on end portions of the plurality of word lines in the interface area; and
a routing wiring line arranged on the word line contact in the interface area, and arranged at a same vertical level as the landing pads.