Mechanisms for fabricating micro-LEDs
In some embodiments, methods for fabricating micro-LEDs may include bonding a semiconductor wafer to a Complementary Metal-Oxide-Semiconductor (CMOS) wafer via one or more adhesive layers, etching the LED epilayer and the one or more adhesive layers to form a plurality of micro-LED structures, and fabricating an electrode layer on the plurality of micro-LED structures. The semiconductor wafer may include an LED epilayer including an n-GaN layer, a p-GaN layer, and an active layer positioned between the n-GaN layer and the p-GaN layer. Prior to the bonding of the semiconductor layer to the CMOS wafer, a stress release pattern may be formed in the LED epilayer. The stress release pattern may include a plurality of geometrical shapes (e.g., squares, rectangles, hexagons, rings, etc.) that may facilitate the release of mechanical stresses induced during the subsequent processing of the semiconductor wafer and/or the fabrication of the micro-LEDs.
1 . A method, comprising:
bonding a semiconductor wafer to a Complementary Metal-Oxide-Semiconductor (CMOS) wafer via one or more adhesive layers, wherein the semiconductor wafer comprises a first substrate, an LED epilayer formed on the first substrate, and a stress release pattern that divides the LED epilayer into a plurality of portions, and wherein the CMOS wafer comprises a second substrate and a plurality of interconnects formed on the second substrate;
etching the LED epilayer and the one or more adhesive layers to form a plurality of micro-LED structures;
fabricating a dielectric layer on the plurality of micro-LED structures; and
fabricating an electrode layer on the plurality of micro-LED structures, wherein fabricating the electrode layer comprises fabricating a layer of a conductive material on the dielectric layer and top surfaces of the plurality of micro-LED structures.
2 . The method of claim 1 , wherein the LED epilayer comprises a plurality of epitaxial layers of gallium nitride.
3 . The method of claim 1 , wherein a dimension of the first substrate is equal to or greater than 6 inches.
4 . The method of claim 3 , wherein a dimension of the second substrate is equal to or greater than 6 inches.
5 . The method of claim 3 , wherein each of the plurality of micro-LED structures is fabricated on a respective interconnect of the plurality of interconnects.
6 . The method of claim 1 , wherein the electrode layer is fabricated on the dielectric layer and the plurality of micro-LED structures.
7 . A method, comprising:
fabricating a stress release pattern in a semiconductor wafer by etching at least a portion of an LED epilayer of the semiconductor wafer, wherein the stress release pattern divides the LED epilayer into a plurality of portions;
bonding the semiconductor wafer to a Complementary Metal-Oxide-Semiconductor (CMOS) wafer via one or more adhesive layers, wherein the semiconductor wafer comprises a first substrate, wherein the LED epilayer is formed on the first substrate, and wherein the CMOS wafer comprises a second substrate and a plurality of interconnects formed on the second substrate;
etching the LED epilayer and the one or more adhesive layers to form a plurality of micro-LED structures; and
fabricating an electrode layer on the plurality of micro-LED structures.
8 . The method of claim 7 , wherein the stress release pattern comprises one or more geometrical shapes that divide the LED epilayer into a plurality of segments.
9 . The method of claim 1 , wherein the plurality of interconnects comprises a plurality of metallic pads or a plurality of metallic vias.
10 . A method, comprising:
bonding a semiconductor wafer to a Complementary Metal-Oxide-Semiconductor (CMOS) wafer via one or more adhesive layers, wherein the semiconductor wafer comprises a first substrate, an LED epilayer formed on the first substrate, and a stress release pattern that divides the LED epilayer into a plurality of portions, and wherein the CMOS wafer comprises a second substrate and a plurality of interconnects formed on the second substrate, wherein bonding the semiconductor wafer to the CMOS wafer via the one or more adhesive layers comprises coating a bonding material on the LED epilayer and the interconnects, wherein at least a portion of the bonding material is coated on the first substrate through the stress release pattern;
etching the LED epilayer and the one or more adhesive layers to form a plurality of micro-LED structures; and
fabricating an electrode layer on the plurality of micro-LED structures.