Clock doubler with correction for output clock cycle and clock duty cycle
A synthesizable clock doubler is disclosed. The clock doubler is implemented using unique combination of logic cells from a standard cell library. At the core of the clock doubler is a high-frequency ring oscillator that generates timing information for clock measurements. Replica ring oscillators are used to generate programmable delays for the correction of the output clock imperfection, such as cycle-to-cycle variation and duty cycle of the doubled clock.
1 . A clock doubler, comprising:
a calibration circuit including a ring oscillator and a first counter, wherein
the ring oscillator is configured to identify timing information for clock measurement associated with an output clock frequency; and
the first counter is configured to output the timing information for calibration of a clock providing an input clock frequency;
a delay circuit including a replica ring oscillator and a second counter, wherein
the replica ring oscillator is configured to determine a delay value for correction of the input clock frequency based on a defined delay value, wherein the replica ring oscillator is configured to determine the delay value based on a counter value corresponding to a defined value; and
the second counter is configured to output the delay value for correction of the output clock frequency having a clock frequency that is a multiple of the input clock frequency.
2 . The clock doubler of claim 1 , wherein the timing information includes a clock period and clock pulse width.
3 . The clock doubler of claim 2 , wherein the clock period and clock pulse width are identified based on a number of ring oscillator clock cycles.
4 . The clock doubler of claim 1 , wherein the delay value is further based on the timing information.
5 . The clock doubler of claim 1 , wherein correction of the output clock frequency includes at least one of correction of a doubled clock cycle-to-cycle variation or a duty cycle of a doubled clock.
6 . The clock doubler of claim 1 , wherein the defined value corresponds to zero.
7 . The clock doubler of claim 1 , wherein the delay circuit includes two replica ring oscillators.
8 . A method of clock cycle correction, comprising:
identifying, via a ring oscillator, timing information for clock measurement associated with an output clock frequency;
outputting, via a first counter, the timing information for calibration of a clock providing an input clock frequency;
determining, via a replica ring oscillator, a delay value for correction of the input clock frequency based on a defined delay value, wherein the replica ring oscillator is configured to determine the delay value based on a counter value corresponding to zero; and
outputting, via the second counter, the delay value for correction of the output clock frequency having a clock frequency that is a multiple of the input clock frequency.
9 . The method of claim 8 , wherein the timing information includes a clock period and clock pulse width.
10 . The method of claim 9 , wherein the clock period and clock pulse width are identified based on a number of ring oscillator clock cycles.
11 . The method of claim 8 , wherein the delay value is further based on the timing information.
12 . The method of claim 8 , wherein correction of the output clock frequency includes at least one of correction of a doubled clock cycle-to-cycle variation or a duty cycle of a doubled clock.
13 . The method of claim 8 , wherein the defined value corresponds to zero.
14 . The method of claim 8 , wherein the delay circuit includes two replica ring oscillators.
15 . A clock doubler, comprising:
means for identifying timing information for clock measurement associated with an output clock frequency; and
means for outputting the timing information for calibration of a clock providing an input clock frequency;
means for determining a delay value for correction of the input clock frequency based on a defined delay value, wherein the delay value is determined based on counter value corresponding to a defined value; and
means for outputting the delay value for correction of the output clock frequency having a clock frequency that is a multiple of the input clock frequency.
16 . The clock doubler of claim 15 , wherein the timing information includes a clock period and clock pulse width.
17 . The clock doubler of claim 16 , wherein the clock period and clock pulse width are identified based on a number of ring oscillator clock cycles.
18 . The clock doubler of claim 16 , wherein the delay value is further based on the timing information.
19 . The clock doubler of claim 16 , wherein correction of the output clock frequency includes at least one of correction of a doubled clock cycle-to-cycle variation or a duty cycle of a doubled clock.
20 . The clock doubler of claim 16 , wherein the defined value corresponds to zero.