IP Library › Granted Patent US 12,488,276
Granted Patent B2
US 12,488,276 · App. 18/369,327 · Granted Dec 2, 2025

Accelerated pattern matching method on a quantum computing system

Inventors: Pradeep Niroula (College Park, MD); Yunseong Nam (North Bethesda, MD)
Assignees: IONQ, INC.; UNIVERSITY OF MARYLAND
G06N10/80G06F9/30032G06F9/30101G06N10/20
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Quick Facts
Patent No.
US 12,488,276
App. No.
18/369,327
Filed
Sep 18, 2023
Granted
Dec 2, 2025
Kind
B2
Art Unit
2851
USPC
716/100
Abstract

A method of determining a pattern in a sequence of bits using a quantum computing system includes setting a first register of a quantum processor in a superposition of a plurality of string index states, encoding a bit string in a second register of the quantum processor, encoding a bit pattern in a third register of the quantum processor, circularly shifting qubits of the second register conditioned on the first register, amplifying an amplitude of a state combined with the first register in which the circularly shifted qubits of the second register matches qubits of the third register, measuring an amplitude of the first register and determining a string index state of the plurality of string index states associated with the amplified state, and outputting, by use of a classical computer, a string index associated with the first register in the measured state.

Claims (47)

1 . A method of determining a pattern in a sequence of bits using a quantum computing system comprising a classical computer and a quantum processor comprising a plurality of qubits, the method comprising:

circularly shifting qubits of a second register conditioned on a first register in each string index state in a superposition of a plurality of string index states, each of which is associated with a string index;

amplifying an amplitude of a state combined with the first register in a string index state of the plurality of string index states in which the circularly shifted qubits of the second register matches qubits of a third register; and

measuring an amplitude of the first register and determining the string index state of the plurality of string index states associated with the amplified state.

2 . The method according to claim 1 , further comprising:

prior to the circularly shifting of the qubits of the second register,

setting the first register of the quantum processor in the superposition of the plurality of string index states;

encoding a bit string in the second register of the quantum processor; and

encoding a bit pattern in the third register of the quantum processor, and

subsequent to the measuring of the amplitude of the first register,

outputting, by use of the classical computer, the string index associated with the first register in the measured state.

3 . The method according to claim 2 , wherein encoding the bit string in the second register of the quantum processor comprises applying a combination of single-qubit gate operations to the second register of the quantum processor.

4 . The method according to claim 2 , wherein encoding the bit pattern in the third register of the quantum processor comprises applying a combination of single-qubit gate operations to the third register of the quantum processor.

5 . The method according to claim 1 , wherein each qubit of the plurality of qubits comprises a trapped ion having two frequency-separated states.

6 . The method according to claim 5 , further comprising:

preparing the quantum processor in an initial state by setting each trapped ion in the quantum processor in the lower energy state of the two frequency-separated states.

7 . The method according to claim 6 , wherein setting the first register of the quantum processor in the superposition of the plurality of string index states comprises transferring each trapped ion in the first register in a superposition of the two frequency-separated states.

8 . The method according to claim 6 , wherein circularly shifting qubits of the second register conditioned on the first register comprises applying a combination of single-qubit gate operations and two-qubit gate operations to the first and second registers of the quantum processor.

9 . The method according to claim 8 , wherein the two-qubit gate operations comprise controlled-SWAP operations applied to the second register conditioned on the first register.

10 . The method according to claim 8 , wherein the two-qubit gate operations comprise controlled-SWAP operations applied to the second register conditioned on a plurality of ancillary qubits in which the first register is copied by fan-out CNOT operations applied on the plurality of ancillary qubits conditioned on the first register.

11 . The method according to claim 5 , wherein amplifying the state combined with the first register in the string index state of the plurality of string index states in which the circularly shifted qubits of the second register matches qubits of the third register comprises applying a combination of single-qubit gate operations and two-qubit gate operations to the second and third registers of the quantum processor.

12 . A quantum computing system, comprising:

a quantum processor comprising a plurality of qubits, each qubit of the plurality of qubits comprising a trapped ion having two frequency-separated states;

one or more lasers configured to emit a laser beam, which is provided to trapped ions in the quantum processor;

a classical computer; and

a system controller configured to:

circularly shift qubits of a second register conditioned on a first register in each string index state in a superposition of a plurality of string index states, each of which is associated with a string index;

amplify an amplitude of a state combined with the first register in a string index state of the plurality of string index states in which the circularly shifted qubits of the second register matches qubits of a third register; and

measure an amplitude of the first register and determining the string index state of the plurality of string index states associated with the amplified state.

13 . The quantum computing system according to claim 12 , wherein the system controller is further configured to:

prior to the circularly shifting of the qubits of the second register,

set the first register of the quantum processor in a superposition of the plurality of string index states, each of which is associated with a string index, wherein the quantum processor comprises the plurality of qubits;

encode a bit string in the second register of the quantum processor; and

encode a bit pattern in the third register of the quantum processor, and

the classical computer is further configured to:

subsequent to the measuring of the amplitude of the first register,

output the string index associated with the first register in the measured state.

14 . The quantum computing system according to claim 13 , wherein

encoding the bit string in the second register of the quantum processor comprises applying a combination of single-qubit gate operations to the second register of the quantum processor, and

encoding the bit pattern in the third register of the quantum processor comprises applying a combination of single-qubit gate operations to the third register of the quantum processor.

15 . The quantum computing system according to claim 12 , wherein the system controller is further configured to:

prepare the quantum processor in an initial state by setting each trapped ion in the quantum processor in the lower energy state of the two frequency-separated states.

16 . The quantum computing system according to claim 12 , wherein setting the first register of the quantum processor in the superposition of the plurality of string index states comprises transferring each trapped ion in the first register in a superposition of the two frequency-separated states.

17 . The quantum computing system according to claim 12 , wherein circularly shifting qubits of the second register conditioned on the first register comprises applying, by the system controller, a combination of single-qubit gate operations and two-qubit gate operations to the first and second registers of the quantum processor.

18 . The quantum computing system according to claim 17 , wherein the two-qubit gate operations comprise controlled-SWAP operations applied to the second register conditioned on the first register.

19 . The quantum computing system according to claim 17 , wherein the two-qubit gate operations comprise controlled-SWAP operations applied to the second register conditioned on a plurality of ancillary qubits in which the first register is copied by fan-out CNOT operations applied on the plurality of ancillary qubits conditioned on the first register.

20 . The quantum computing system according to claim 12 , wherein amplifying the state combined with the first register in the string index state of the plurality of string index states in which the circularly shifted qubits of the second register matches qubits of the third register comprises applying, by the system controller, a combination of single-qubit gate operations and two-qubit gate operations to the second and third registers of the quantum processor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2024
From: NAM, YUNSEONG
To: IONQ, INC.
Reel/Frame 066401/0995 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2024
From: NIROULA, PRADEEP
To: MARYLAND, UNIVERSITY OF
Reel/Frame 066402/0020 →
Continuity (3)
Continuation 17313671 · May 6, 2021
Provisional Application 63031385 · May 28, 2020
Related Publication 20240013078A1 · Jan 11, 2024
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