Supporting circuits with a single local oscillator
A digital signal processing circuit includes an analog gain compensator that compensates for an analog gain of a baseband signal including a plurality of component carriers (CCs) to output a compensated baseband signal; an analog-to-digital converter (ADC) that converts the compensated baseband signal into a first digital signal; a plurality of filtering circuits that generate a second digital signal from the first digital signal; and a control circuit. Each filtering circuit sequentially filters the first digital signal so that a corresponding one of the second digital signals retains one CC among the CCs, compensates for a digital gain, and a performs down-sampling. The control circuit generates an analog gain control signal for controlling the analog gain based on the second digital signals and a digital gain control signal for controlling the digital gain.
1 . A digital signal processing circuit comprising:
an analog gain compensator configured to compensate for an analog gain of a baseband signal including a plurality of component carriers (CCs) to output a compensated baseband signal;
an analog-to-digital converter (ADC) configured to convert the compensated baseband signal into a first digital signal;
a plurality of filtering circuits configured to generate a plurality of second digital signals from the first digital signal, where each filtering circuit sequentially filters the first digital signal so that a corresponding one of the second digital signals retains one CC among the CCs, compensates for a digital gain, and performs down-sampling; and
a first control circuit configured to generate an analog gain control signal for controlling the analog gain based on the plurality of second digital signals and a digital gain control signal for controlling the digital gain based on the plurality of second digital signals,
wherein the first control circuit comprises:
a plurality of logic circuits connected to each of the plurality of filtering circuits and configured to perform a Fourier transform on a corresponding one of the second digital signals to output a plurality of Fourier transformed digital signals;
a plurality of power measurement circuits configured to measure a power value from each of the plurality of Fourier-transformed digital signals to generate a plurality of power values; and
a second control circuit configured to generate the analog gain control signal and the digital gain control signal based on the plurality of power values.
2 . The digital signal processing circuit of claim 1 , wherein each of the plurality of filtering circuits comprises:
a mixer configured to output a frequency-shifted digital signal from the first digital signal by shifting the one CC to a target frequency;
a filter configured to output a filtered digital signal from which CCs other than the one CC are removed from the frequency-shifted digital signal by filtering the frequency-shifted digital signal based on the target frequency;
a digital gain compensator configured to output a compensated digital signal by compensating for a digital gain of the filtered digital signal based on the digital gain control signal; and
a decimation filter configured to output a corresponding one of the second digital signals by filtering and down-sampling the compensated digital signal corresponding to a system bandwidth of the one CC.
3 . The digital signal processing circuit of claim 2 , wherein the target frequency includes a direct current (DC) frequency.
4 . The digital signal processing circuit of claim 2 , wherein the mixer is configured to shift the one CC to the target frequency using a frequency corresponding to the one CC generated by a local oscillator (LO).
5 . The digital signal processing circuit of claim 1 , wherein the one CC is different for each of the plurality of filtering circuits.
6 . The digital signal processing circuit of claim 5 , wherein the digital gain control signal is generated for each of the plurality of filtering circuits.
7 . The digital signal processing circuit of claim 5 , wherein the digital gain control signal controls each of the plurality of filtering circuits to allow a digital gain of the one CC to be compensated with a target digital gain.
8 . The digital signal processing circuit of claim 2 , wherein the filter is a low-pass-filter (LPF).
9 . The digital signal processing circuit of claim 2 , wherein a signal-to-quantization noise ratio (SQNR) of at least one of the second digital signals is greater than a SQNR of the compensated digital signal.
10 . The digital signal processing circuit of claim 1 , wherein the second digital signals are generated to satisfy a target power for each of the plurality of CCs.
11 . A digital filter comprising:
a plurality of filtering circuits each configured to process one component carrier (CC) of a plurality of CCs, wherein each of the plurality of filtering circuits comprises:
a mixer configured to output a frequency-shifted digital signal by shifting one CC among the plurality of CCs from a first digital signal converted from a baseband signal to a target frequency;
a filter configured to output a filtered digital signal from which CCs other than the one CC are removed from the frequency-shifted digital signal by filtering the frequency-shifted digital signal based on the target frequency;
a digital gain compensator configured to output a compensated digital signal by compensating for a digital gain of the filtered digital signal; and
a decimation filter configured to output a second digital signal by filtering and down-sampling the compensated digital signal corresponding to a system bandwidth of the one CC;
a plurality of logic circuits connected to each of the plurality of filtering circuits and configured to perform a Fourier transform on a corresponding one of the second digital signals to output a plurality of Fourier transformed digital signals;
a plurality of power measurement circuits configured to measure a power value from each of the plurality of Fourier-transformed digital signals to generate a plurality of power values; and
a control circuit configured to generate a digital gain control signal for controlling the digital gain based on the plurality of power values.
12 . The digital filter of claim 11 , wherein the one CC is different for each of the plurality of filtering circuits.
13 . The digital filter of claim 11 , wherein the target frequency includes a direct current (DC) frequency.
14 . The digital filter of claim 11 , wherein the mixer is configured to shift the one CC to the target frequency using a frequency corresponding to the one CC generated by a local oscillator (LO).
15 . The digital filter of claim 11 , wherein the digital gain compensator is configured to operate based on a digital gain control signal generated for each of the plurality of filtering circuits.
16 . The digital filter of claim 11 , wherein a signal-to-quantization noise ratio (SQNR) of the second digital signal is greater than a SQNR of the compensated digital signal.
17 . The digital filter of claim 11 , wherein the second digital signal is generated to satisfy a target power for each of the plurality of CCs.
18 . A receiver comprising:
a low-noise amplifier (LNA) configured to amplify a radio frequency (RF) signal including a plurality of component carriers (CCs) received from an antenna;
a receiving circuit configured to process the RF signal using an oscillator signal generated by a single local oscillator (LO) to output a baseband signal; and
a digital signal processing circuit configured to digitally process the baseband signal,
wherein the digital signal processing circuit comprises:
an analog gain compensator configured to compensate for an analog gain of a baseband signal to output a compensated baseband signal;
an analog-to-digital converter (ADC) configured to convert the compensated baseband signal into a first digital signal;
a plurality of filtering circuits configured to generate a plurality of second digital signals from the first digital signal, where each filtering circuit sequentially filters the first digital signal so that a corresponding one of the second digital signals retains one CC among the CCs, compensates for a digital gain, and performs down-sampling; and
a first control circuit configured to generate an analog gain control signal for controlling the analog gain based on the plurality of second digital signals and a digital gain control signal for controlling the digital gain based on the plurality of second digital signals,
wherein the first control circuit comprises:
a plurality of logic circuits connected to each of the plurality of filtering circuits and configured to perform a Fourier transform on a corresponding one of the second digital signals to output a plurality of Fourier transformed digital signals;
a plurality of power measurement circuits configured to measure a power value from each of the plurality of Fourier-transformed digital signals to generate a plurality of power values; and
a second control circuit configured to generate the analog gain control signal and the digital gain control signal based on the plurality of power values.
19 . The receiver of claim 18 , wherein the plurality of filtering circuits each are configured to process one CC of the plurality of CCs.