Interface, electronic device, and communication system
An interface includes a first functional part and a second functional part. The first functional part is configured to implement processing dependent on a medium access control (MAC) rate, and the second functional part is configured to implement processing independent of the MAC rate.
1 . A transmitting device, comprising:
a transcode circuit;
an encode and rate matching circuit directly connected to the transcode circuit;
a data block distribution circuit directly connected to the transcode circuit; and
multiple groups of circuits coupled to the data block distribution circuit, wherein each of the multiple groups of circuits comprises a scramble circuit, an alignment marker insertion circuit, and a forward error correction (FEC) encode circuit, the scramble circuit of each of the multiple groups of circuits is directly connected to the data block distribution circuit.
2 . The transmitting device according to claim 1 , wherein a sum of rates of the multiple groups of circuits matches a medium access control (MAC) rate of the encode and rate matching circuit.
3 . The transmitting device according to claim 1 , further comprising a physical coding sublayer (PCS) circuit configured to perform interleaving on a first data based on an FEC symbol, wherein the first data is output by the FEC encode circuit.
4 . The transmitting device according to claim 3 , further comprising a physical medium attachment (PMA) circuit configured to interleave second data, wherein the second data is obtained after interleaving is performed on the first data based on the FEC symbol.
5 . The transmitting device according to claim 1 , wherein the FEC encode circuit is a first-level FEC encode circuit in concatenated FEC encode circuits.
6 . The transmitting device according to claim 5 , wherein the first-level FEC encode circuit is configured to perform Reed-Solomon (RS) FEC.
7 . The transmitting device according to claim 1 , wherein the transmitting device further comprises a reconciliation sublayer circuit coupled to the encode and rate matching circuit via a media independent interface (MII).
8 . The transmitting device according to claim 2 , wherein the MAC rate is 1.6 Tb/s, the multiple groups of circuits comprise two groups of circuits, and a rate of each of the two groups of circuits is 800 Gb/s.
9 . The transmitting device according to claim 1 , wherein the transcode circuit is configured to perform a 64B/66B-to-256B/257B transcode.
10 . A receiving device, comprising:
a reverse transcode circuit;
a decode and rate matching circuit directly connected to the reverse transcode circuit;
a data block distribution circuit directly connected to the reverse transcode circuit; and
multiple groups of circuits coupled to the data block distribution circuit, wherein each of the multiple groups of circuits comprises a descramble circuit, an alignment marker removal circuit, and a forward error correction (FEC) decode circuit, the descramble circuit of each of the multiple groups of circuits is directly connected to the data block distribution circuit.
11 . The receiving device according to claim 10 , wherein a sum of rates of the multiple groups of circuits matches a medium access control (MAC) rate of the decode and rate matching circuit.
12 . The receiving device according to claim 10 , further comprising an alignment lock circuit.
13 . The receiving device according to claim 10 , wherein the FEC decode circuit is a first-level FEC decode circuit in concatenated FEC decode circuits.
14 . The receiving device according to claim 10 , further comprising a reconciliation sublayer circuit coupled to the decode and rate matching circuit via a media independent interface (MII).
15 . The receiving device according to claim 11 , wherein the MAC rate is 1.6 Tb/s the multiple groups of circuits comprise two groups of circuits, and a rate of each of the two groups of circuits is 800 Gb/s.
16 . The receiving device according to claim 10 , wherein the reverse transcode circuit is configured to perform a 256B/257B-to-64B/66B reverse transcode.
17 . A transmission method, comprising:
encoding and rate matching on first data to obtain second data;
transcoding the second data to obtain transcoded data;
distributing the transcoded data to obtain a first portion of the transcoded data and a second portion of the transcoded data;
scrambling, by a first group of circuits, the first portion of the transcoded data to obtain first scrambled data;
inserting, by the first group of circuits, a first alignment mark into the first scrambled data to obtain first alignment data;
encoding, by the first group of circuits, according to a forward error correction (FEC) code, the first alignment data to obtain first encoded data;
scrambling, by a second group of circuits, the second portion of the transcoded data to obtain second scrambled data;
inserting, by the second group of circuits, a second alignment mark into the second scrambled data to obtain second alignment data; and
encoding, by the second group of circuits, according to the FEC code, the second alignment data to obtain second encoded data.
18 . The method according to claim 17 , wherein a sum of rates of the first group of circuits and the second group of circuits matches a medium access control (MAC) rate for the first data.
19 . The method according to claim 17 , wherein the method further comprises:
interleaving the first encoded data based on an FEC symbol at a physical coding sublayer (PCS) to obtain first symbol interleaved data; and
interleaving the second encoded data based on the FEC symbol at the PCS to obtain second symbol interleaved data.
20 . The method according to claim 19 , wherein the method further comprises:
interleaving the first symbol interleaved data at a physical medium attachment (PMA) to obtain first interleaved data; and
interleaving the second symbol interleaved data at the PMA to obtain second interleaved data.
21 . The method according to claim 17 , wherein the encoding process according to the FEC code is a first-level FEC encode process in concatenated FEC encoding processes.
22 . The method according to claim 21 , wherein the first-level FEC encoding process is configured to perform Reed-Solomon (RS) FEC.
23 . The method according to claim 18 , wherein the MAC rate is 1.6 Tb/s and a rate of the first group of circuits is 800 Gb/s and a rate of the second group of circuits is 800 Gb/s.
24 . The method according to claim 17 , wherein the transcoding is configured to perform a 64B/66B-to-256B/257B transcode.
25 . A transmission method, comprising:
decoding, by a first group of circuits, according to a forward error correction (FEC) code, first data to obtain first decoded data;
removing, by the first group of circuits, a first alignment mark from the first decoded data to obtain first alignment removal data;
descrambling, by the first group of circuits, the first alignment removal data to obtain the first descrambled data;
decoding, by a second group of circuits, according to the FEC code, second data to obtain second decoded data;
removing, by the second group of circuits, a second alignment mark from the second decoded data to obtain second alignment removal data;
descrambling, by the second group of circuits, the second alignment removal data to obtain the second descrambled data;
distributing the first descrambled data and the second descrambled data to obtain distributed data;
reverse transcoding the distributed data to obtain reverse transcoded data; and
decoding and rate matching on the reverse transcoded data to obtain third data.
26 . The method according to claim 25 , wherein a sum of rates of the first group of circuits and the second group of circuits matches a medium access control (MAC) rate for the third data.
27 . The method according to claim 25 , wherein the decoding process according to the FEC code is a first-level FEC decode process in concatenated FEC decoding processes.
28 . The method according to claim 26 , wherein the MAC rate is 1.6 Tb/s and a rate of the first group of circuits is 800 Gb/s and a rate of the second group of circuits is 800 Gb/s.
29 . The method according to claim 25 , wherein the reverse transcoding is configured to perform a 256B/257B-to-64B/66B reverse transcode.