Semiconductor device and processes for making same
The disclosure provides a semiconductor package having an isolation structure comprising an isolation trench filled with dielectric material, where the isolation structure traverses the thickness of the isolated semiconductor dies.
1 . A semiconductor device, comprising:
at least two semiconductor dies, each of the at least two semiconductor dies includes a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate;
a layer of a first dielectric material disposed on a top surface of the epitaxial layer; and
an isolation structure electrically isolating two semiconductor dies of the at least two semiconductor dies, the isolation structure comprising an isolation trench extended from the top surface of the epitaxial layer into the semiconductor substrate, and the isolation trench being filled with the first dielectric material and covered by the layer of the first dielectric material;
wherein the semiconductor device further comprises a channel within the at least two semiconductor dies, and a layer of metal is plated in the channel and on a bottom surface of the semiconductor substrate.
2 . The semiconductor device of claim 1 , wherein the at least two semiconductor dies are fabricated with circuit elements on the epitaxial layer such that terminal nodes of the circuit elements are accessible on a top surface of the at least two semiconductor dies.
3 . The semiconductor device of claim 1 , further comprising a second dielectric material disposed on a bottom surface of the semiconductor substrate and encapsulating the at least two semiconductor dies.
4 . The semiconductor device of claim 3 , wherein the first dielectric material is different from the second dielectric material.
5 . The semiconductor device of claim 3 , wherein the first dielectric material is same as the second dielectric material.
6 . The semiconductor device of claim 3 , wherein the isolation structure comprises a first isolation structure and a second isolation structure, the first isolation structure is filled with the first dielectric material and the second isolation structure is filled with the second dielectric material, and the first dielectric material is different from the second dielectric material.
7 . The semiconductor device of claim 6 , wherein the first isolation structure comprises a plurality of sub-trenches.
8 . The semiconductor device of claim of claim 1 , wherein the isolation trench is between the top surface of the epitaxial layer and a bottom surface of the semiconductor substrate, and the first dielectric material in the isolation trench is connected to the layer of the first dielectric material on the epitaxial layer.
9 . The semiconductor device of claim of claim 1 , wherein the channel extends from a bottom surface of the semiconductor substrate into the semiconductor substrate.
10 . A semiconductor device, comprising:
two semiconductor dies adjacent to each other, each of the two semiconductor dies including a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate;
a layer of a first dielectric material disposed on a bottom surface of the semiconductor substrate; and
an isolation structure between the two semiconductor dies and electrically isolating the two semiconductor dies from each other, the isolation structure comprising a first isolation trench extended from the bottom surface of the semiconductor substrate into the semiconductor substrate, and the first isolation trench being filled with the first dielectric material and covered by the layer of the first dielectric material;
wherein the isolation structure comprises:
a first isolation structure comprising the first isolation trench filled with the first dielectric material; and
a second isolation structure connected to the first isolation structure along a thickness of the two semiconductor dies, the second isolation structure comprising a second isolation trench filled with a second dielectric material, and the second isolation trench extending from a top surface of the epitaxial layer into the semiconductor substrate;
wherein the first isolation trench has a width different from that of the second isolation trench.
11 . The semiconductor device of claim 10 , wherein the second isolation trench comprises a plurality of separated sub-trenches.
12 . The semiconductor device of claim 10 , wherein the first dielectric material is different from the second dielectric material.
13 . The semiconductor device of claim 10 , wherein each of the two semiconductor dies further comprises a channel extending from the bottom surface of the semiconductor substrate into the semiconductor substrate; and a layer of metal is plated in the channel and on the bottom surface of the semiconductor substrate.
14 . The semiconductor device of claim 13 , wherein the channel comprises a plurality of sub-channels.
15 . The semiconductor device of claim 13 , wherein the channel is extended through the semiconductor substrate into the epitaxial layer.
16 . The semiconductor device of claim of claim 10 , wherein the two semiconductor dies are fabricated with circuit elements on the epitaxial layer, with terminal nodes of the circuit elements accessible on a top surface of the two semiconductor dies.
17 . A semiconductor device, comprising:
two semiconductor dies adjacent to each other, each of the two semiconductor dies including a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate;
an isolation structure between the two semiconductor dies and electrically isolating the two semiconductor dies from each other, the isolation structure comprising:
a first isolation trench extending from a top surface of the epitaxial layer into the semiconductor substrate; and
a second isolation trench extending from a bottom surface of the semiconductor substrate into the semiconductor substrate and connected to the first isolation trench, wherein the first isolation trench is filled with a first dielectric material and the second isolation trench is filled with a second dielectric material.
18 . The semiconductor device of claim 17 , wherein the first isolation trench and the second isolation trench have different widths.
19 . The semiconductor device of claim 17 , wherein the first isolation trench comprises a plurality of separated sub-trenches.
20 . The semiconductor device of claim 17 , wherein the two semiconductor dies are fabricated with circuit elements on the epitaxial layer, with terminal nodes of the circuit elements accessible on a top surface of the two semiconductor dies.