Pixel cell circuitry for image sensors
An image sensor comprising a semiconductor substrate and pixel cell circuitry is described. The semiconductor substrate includes a first side and a second side opposite the first side. The pixel cell circuitry is disposed proximate to the first side of the semiconductor substrate. The pixel cell circuitry includes an arrangement of individual groups of components, each including a reset gate, a source-follower gate, and a row select gate. The individual groups of components included in the pixel cell circuitry includes a first group and a second group adjacent to the first group, and wherein the source-follower gate of the first group is disposed adjacent to the source-follower gate of the second group.
1 . An image sensor, comprising:
a semiconductor substrate including a first side and a second side opposite of the first side;
pixel cell circuitry disposed proximate to the first side of the semiconductor substrate, wherein the pixel cell circuitry includes an arrangement of individual groups of components, each including a reset gate, a source-follower gate, and a row select gate,
wherein the individual groups of components includes a first group and a second group adjacent to the first group, and wherein the source-follower gate of the first group is disposed adjacent to the source-follower gate of the second group.
2 . The image sensor of claim 1 , wherein the arrangement of the individual groups of components included in the pixel cell circuitry is mirror symmetric about a first axis.
3 . The image sensor of claim 2 , wherein the arrangement of the individual groups of components included in the pixel cell circuitry is mirror symmetric about a second axis, and wherein the second axis is orthogonal to the first axis.
4 . The image sensor of claim 3 , wherein the arrangement of the individual groups of components included in the pixel cell circuitry is further mirror symmetric about a diagonal axis extending between the first axis and the second axis.
5 . The image sensor of claim 2 , wherein the first axis is parallel with at least one of a power rail or a bit line disposed proximate to the semiconductor substrate of the image sensor.
6 . The image sensor of claim 1 , wherein the individual groups of components of the pixel cell circuitry are arranged in or on respective portions of the semiconductor substrate to form a pixel circuitry array, the respective portions of the semiconductor substrate arranged in rows and columns such that an adjacent set of four of the individual groups of components span two adjacent rows included in the rows and two adjacent columns included in the columns and wherein the adjacent set collectively form pixel transistors for a full-color image pixel of the image sensor.
7 . The image sensor of claim 1 , wherein the individual groups of components of the pixel cell circuitry are arranged in or on respective portions of the semiconductor substrate to form a pixel circuitry array, the respective portions of the semiconductor substrate arranged in rows and columns such that an adjacent set of four of the individual groups of components span two adjacent rows included in the rows and two adjacent columns included in the columns, and wherein each of the reset gate, the source-follower gate, and the row select gate of the adjacent set collectively surround a region of the semiconductor substrate having a first lateral area.
8 . The image sensor of claim 7 , wherein the first lateral area is greater than a second lateral area of any one of the reset gate, the source-follower gate, or the row select gate included in each of the individual groups of components.
9 . The image sensor of claim 7 , further comprising additional circuitry associated with the image sensor formed in or on the region of the semiconductor substrate having the first lateral area, and wherein the additional circuitry includes at least one of a switchable conversion gain circuit or a storage node of the image sensor.
10 . The image sensor of claim 1 , wherein the individual groups of components further includes a third group and a fourth group respectively arranged adjacent to the first group and the second group to form a two-by-two array included in the individual groups of components, wherein the third group is adjacent to the fourth group wherein the source-follower gate and the row select gate of both the first group and the second group are arranged along a first direction, wherein the source-follower gate and the row select gate of the third group and the fourth group are aligned along a second direction separated from, but parallel to, the first direction.
11 . The image sensor of claim 10 , wherein the first direction and the second direction are orthogonal to the first axis.
12 . The image sensor of claim 1 , wherein the source-follower gate of the first group and the source-follower gate of the second group are coupled to a common junction region formed in the semiconductor substrate.
13 . The image sensor of claim 1 , wherein the reset gate of the first group is disposed adjacent to the reset gate of the second group.
14 . The image sensor of claim 13 , wherein the source-follower gate of the first group and the source-follower gate of the second group are arranged along a first direction, wherein the reset gate of the first group and the source-follower gate of the first group are arranged along a second direction orthogonal to the first direction.
15 . The image sensor of claim 1 , wherein the individual groups of components further includes a third group and a fourth group respectively arranged adjacent to the first group and the second group,
wherein the source-follower gate of the first group and the second group are arranged along a first direction,
wherein the source-follower gate of the third group and the source-follower gate of the fourth group are arranged along a second direction separated from but parallel to the first direction,
wherein the source-follower gate of the first group and the source-follower gate of the third group are arranged along a third direction orthogonal to the first direction, and
wherein the source-follower gate of the second group and the source-follower gate of the fourth group are arranged along a fourth direction separated from but parallel to the third direction.
16 . The image sensor of claim 1 , further comprising threshold voltage adjustment regions disposed within the semiconductor substrate including:
a first threshold voltage adjustment region disposed between the source-follower gate of the first group and the second side of the semiconductor substrate; and
a second threshold voltage adjustment region disposed between the source-follower gate of the second group and the second side of the semiconductor substrate,
wherein the source-follower gate of the first group and the source-follower gate of the second group are arranged along a first direction, and wherein formation of the first threshold voltage adjustment region and the second threshold voltage adjustment region is achieved using a common implantation window such that doping concentrations of the first threshold voltage adjustment region and the second threshold voltage adjustment region are equivalent.
17 . The image sensor of claim 1 , wherein the individual groups of components further includes a third group arranged adjacent to first group such that the first group is disposed between the second group and the third group, wherein the individual groups of components each further comprises a ground contact region, and wherein the ground contact region of the first group is disposed adjacent to the ground contact region of the third group.
18 . The image sensor of claim 17 , wherein the source-follower gate of the first group, the source-follower gate of the second group, the source-follower gate of the third group, the row select gate of the first group, the row select gate of the second group, and the row select gate of the third group are disposed along a first common direction, wherein the reset gate of the first group, the reset gate of the second group, the reset gate of the third group, the ground contact region of the first group, the ground contact region of the second group, and the ground contact region of the third group are disposed along a second common direction separated from but parallel to the first common direction.
19 . The image sensor of claim 17 , further comprising a ground shield bus line disposed between a first bit line and a second bit line, wherein the ground contact region of the first group and the ground contact region of the third group are both coupled to the ground shield bus line.
20 . The image sensor of claim 17 , wherein the ground contact region of the first group extends from the ground contact region of the third group to form a shared ground contact region.
21 . The image sensor of claim 1 , wherein the individual groups of components further includes a third group and a fourth group respectively arranged adjacent to the first group and the second group to form a two-by-two array included in the individual groups of components, wherein the source-follower gate of the first group is positioned adjacent to both the source-follower gate of the second group and the source-follower gate of the third group, and wherein the source-follower gate of the fourth group is positioned adjacent to both the source-follower gate of the second group and the source-follower gate of the third group.