Endurance hints for tiered memory

1 . An electronic apparatus, comprising:

one or more substrates; and

a controller coupled to the one or more substrates, the controller including circuitry to:

control access to a persistent media; and

manage an endurance of the persistent media based on one or more endurance hints from a processor;

wherein:

the one or more endurance hints are to be based on an endurance-hint instruction which is to comprise both an identifier of an address range and an identifier of an access mode; and

based on an execution of the endurance-hint instruction with the processor, the circuitry is to register a hint that the address range is to be accessed according to the access mode.

2 . The electronic apparatus of claim 1 , wherein the circuitry is to:

delay a write-back to the persistent media based on the hint that the address range is to be accessed according to the access mode.

3 . The electronic apparatus of claim 1 , wherein the circuitry is further to:

provide an interface to receive the one or more endurance hints from the processor.

4 . The electronic apparatus of claim 1 , wherein:

the endurance-hint instruction is a first endurance-hint instruction; and

based on an execution of a second endurance-hint instruction with the processor, the circuitry is further to deregister the hint that the address range is to be accessed according to the access mode.

5 . The electronic apparatus of claim 1 , wherein the circuitry to manage the endurance of the persistent media based on the one or more endurance hints comprises the circuitry to:

provide relatively more priority to buffer access requests to the address range identified by the endurance hint.

6 . The electronic apparatus of claim 1 , wherein the circuitry to manage the endurance of the persistent media based on the one or more endurance hints comprises the circuitry to:

provide relatively more priority to cache lines that are pending to be flushed that belong to the address range identified by the endurance hint.

7 . The electronic apparatus of claim 1 , wherein the circuitry to manage the endurance of the persistent media based on the one or more endurance hints comprises the circuitry to:

host the address range identified by the endurance hint on a scratchpad memory.

8 . An electronic system, comprising:

a processor to perform an execution of an endurance-hint instruction which is to comprise both an identifier of an address range and an identifier of an access mode;

a tiered memory that includes one or more tiers of a persistent media; and

a controller communicatively coupled to the processor and the tiered memory, the controller including first circuitry to:

control access to the tiered memory; and

provide one or more endurance hints to the one or more tiers of the persistent media;

wherein:

the one or more endurance hints are to be based on the execution of the endurance-hint instruction; and

based on the execution of the endurance-hint instruction, the first circuitry is to register a hint that the address range is to be accessed according to the access mode.

9 . The electronic system of claim 8 , wherein:

the endurance-hint instruction is a first endurance-hint instruction; and

based on an execution of a second endurance-hint instruction with the processor, the first circuitry is further to deregister the hint that the address range is to be accessed according to the access mode.

10 . The electronic system of claim 9 , wherein at least one tier of the one or more tiers of the persistent media includes second circuitry to:

manage an endurance of the at least one tier based on the address range and the access mode identified by the hint that the address range is to be accessed according to the access mode.

11 . The electronic system of claim 10 , wherein the second circuitry to manage the endurance of the at least one tier comprises the second circuitry to:

delay a write-back to media at the address range identified by the hint.

12 . The electronic system of claim 8 , wherein the first circuitry is further to:

monitor memory traffic for the tiered memory; and

determine an endurance hint for the one or more tiers of the persistent media based on an analysis of the monitored memory traffic.

13 . A method of controlling memory, the method comprising:

controlling access to a persistent media; and

managing an endurance of the persistent media based on one or more endurance hints from a processor;

wherein:

the one or more endurance hints are based on an endurance-hint instruction which comprises both an identifier of an address range and an identifier of an access mode; and

based on an execution of the endurance-hint instruction with the processor, a controller coupled to the processor registers a hint that the address range is to be accessed according to the access mode.

14 . The method of claim 13 , further comprising:

delaying a write-back to the persistent media based on the hint that the address range is to be accessed according to the access mode.

15 . The method of claim 13 , further comprising:

providing an interface to receive the one or more endurance hints from the processor.

16 . The method of claim 13 , wherein:

the endurance-hint instruction is a first endurance-hint instruction; and

based on an execution of a second endurance-hint instruction with the processor, the controller further deregisters the hint that the address range is to be accessed according to the access mode.

17 . The method of claim 16 , wherein managing the endurance of the persistent media based on the one or more endurance hints comprises:

providing relatively more priority to buffer access requests to the address range identified by the hint the address range is to be accessed according to the access mode.

18 . The method of claim 16 , further comprising:

hosting the address range identified by the hint on a scratchpad memory.