IP Library › Granted Patent US 12,493,704
Granted Patent B2
US 12,493,704 · App. 18/436,899 · Granted Dec 9, 2025

Protecting a non-volatile solid-state memory from an unauthorized access

Inventors: Cesar Augusto Rodriguez Bravo (Alajuela, CR); David Alonso Campos Batista (Aurora, CR); Thomas Brackhahn (Garches, FR)
Assignee: Kyndryl, Inc.
G06F21/62G06F21/79G06F2221/2143
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Quick Facts
Patent No.
US 12,493,704
App. No.
18/436,899
Granted
Dec 9, 2025
Kind
B2
Abstract

An approach is provided for protecting data stored by a non-volatile solid-state memory from an unauthorized access. In response to a trigger event indicating an increased probability of the unauthorized access, the memory is destroyed by directing through the memory an electric current exceeding a rated current of the memory, and testing an operability of the memory, where the destruction is completed when the test indicates lacking operability of the memory.

Claims (30)

1 . A computer-implemented method of protecting data stored by a non-volatile solid-state memory from an unauthorized access, the method comprising:

in response to a trigger event indicating an increased probability of the unauthorized access, destroying the memory by directing through the memory an electric current exceeding a rated current of the memory; and

in response to directing through the memory the electric current exceeding the rated current of the memory, testing an operability of the memory by directing a command to the memory intended to cause a response from the memory, wherein the destroying is completed when the testing indicates a lacking of an operability of the memory to cause the response.

2 . The method of claim 1 , the destroying comprising a plurality of repetitions of directing the electric current through the memory.

3 . The method of claim 2 , the current being successively increased during the repetitions.

4 . The method of claim 3 , wherein, for each of the repetitions, the current is selected from a predefined set of currents exceeding standard values of the rated current.

5 . The method of claim 1 , the current being generated by discharging a capacitor of a memory device incorporating the memory.

6 . The method of claim 5 , wherein:

the generation of the current further comprises charging the capacitor at a voltage exceeding a rated charging voltage of the capacitor in order to force the capacitor to collect more charge carriers than could be collected by charging the capacitor at the rated charging voltage; and

a higher current density is achieved inside the memory by discharging the capacitor, having been overcharged, through the memory.

7 . The method of claim 1 , the memory being a component of a memory device functionally coupled to a computing device electrically connected to a power source, the method further comprising establishing an electrical connection from the memory device to the power source for generating the current.

8 . The method of claim 7 , the electrical connection between the power source and the computing device being provided by a communications network, wherein the communications network includes a power-over-ethernet connection.

9 . The method of claim 1 , the trigger event being selected from the group consisting of a receipt of a signal indicating an attempt of unauthorized mechanical manipulation of a first computing device incorporating the memory, a receipt of an instruction requiring destruction of the memory, a power-up of the memory device outside a predefined geographic area, a mechanical detachment of the memory from the first computing device, and an establishment of a functional coupling of the memory to a second computing device different from the first computing device.

10 . The method of claim 1 , wherein the destroying is limited to the memory.

11 . A circuitry comprising a memory controller, where the memory controller is configured to control a non-volatile solid-state memory, and protect data stored by the memory from an unauthorized access, the memory controller performing operations comprising:

in response to a trigger event indicating an increased probability of the unauthorized access, destroying the memory by directing through the memory an electric current exceeding a rated current of the memory; and

in response to directing through the memory the electric current exceeding the rated current of the memory, testing an operability of the memory by directing a command to the memory intended to cause a response from the memory, wherein the destroying is completed when the test indicates a lacking of an operability of the memory to cause the response.

12 . The circuitry of claim 11 , the destroying comprising a plurality of repetitions of directing the electric current through the memory.

13 . The circuitry of claim 12 , the current being successively increased during the repetitions.

14 . The circuitry of claim 11 , the current being generated by discharging a capacitor of a memory device incorporating the memory.

15 . The circuitry of claim 11 , wherein the trigger event comprises detecting an attempt of unauthorized mechanical manipulation of a computing device incorporating the memory.

16 . A computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions being executable by a processor functionally coupled to a non-volatile solid-state memory to cause the processor to perform a method of protecting data stored by the memory from an unauthorized access, the method comprising:

in response to a trigger event indicating an increased probability of the unauthorized access, destroying the memory by directing through the memory an electric current exceeding a rated current of the memory; and

in response to directing through the memory the electric current exceeding the rated current of the memory, testing an operability of the memory by directing a command to the memory intended to cause a response from the memory, wherein the destroying is completed when the test indicates a lacking of an operability of the memory to cause the response;

wherein the current is generated by discharging a capacitor of a memory device incorporating the memory;

wherein the generation of the current further comprises charging the capacitor at a voltage exceeding a rated charging voltage of the capacitor in order to force the capacitor to collect more charge carriers than could be collected by charging the capacitor at the rated charging voltage; and

wherein a higher current density is achieved inside the memory by discharging the capacitor, having been overcharged, through the memory.

17 . The computer program product of claim 16 , the destroying comprising a plurality of repetitions of directing the electric current through the memory.

18 . The computer program product of claim 17 , the current being successively increased during the repetitions.

19 . The computer program product of claim 16 , the trigger event being selected from the group consisting of a receipt of a signal indicating an attempt of unauthorized mechanical manipulation of a first computing device incorporating the memory, a receipt of an instruction requiring destruction of the memory, a power-up of the memory device outside a predefined geographic area, a mechanical detachment of the memory from the first computing device, and an establishment of a functional coupling of the memory to a second computing device different from the first computing device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2024
From: RODRIGUEZ BRAVO, CESAR AUGUSTO; CAMPOS BATISTA, DAVID ALONSO; BRACKHAHN, THOMAS
To: KYNDRYL, INC.
Reel/Frame 066422/0373 →
Priority Claims (1)
EP 23315309 · Aug 10, 2023 · regional
Continuity (1)
Related Publication 20250053671A1 · Feb 13, 2025
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