IP Library › Granted Patent US 12,493,783
Granted Patent B2
US 12,493,783 · App. 17/865,792 · Granted Dec 9, 2025

Data processing array

Inventors: Rikki J. Crill (Longmont, CO); Jonathan C. Baiardo (Carbondale, CO); David A. Bruce (Niwot, CO)
Assignee: Look Dynamics, Inc.
G06N3/0675G06N3/045G06N3/08G06N3/084
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,493,783
App. No.
17/865,792
Granted
Dec 9, 2025
Kind
B2
Abstract

A data processing array comprises a plurality of modules, each with a memory, positioned in an array of rows and columns interconnected by a pooling chain that carries data to and receives data from selected ones or groups of the modules. Each modules can also have light modulator elements for transmitting data as light signals and a light sensor for receiving data in the form of modulated light. Pooling switches in the pooling chain between modules open and close the pooling chain lines for selecting and grouping modules. Analog data lines separate from the pooling chain can also carry data to and from the modules. Pooling control lines connected to the switches turn the switches on and off for the selecting and grouping of modules. Module control lines, also separate from the pooling chain, connected to the modules enable various data input, output, and processing by the memory or other components in the module.

Claims (8)

1 . A data processing array, comprising:

an array of modules arranged in a plurality of rows and a plurality of columns, each module in the array comprising a read and write memory;

a pooling chain comprising a first pooling border line extending along a first side of each module in each column in the array and a second pooling border line extending along a second side of each module in the array, wherein the first border line that extends along the first side of each module intersects and connects with the second border line that extends along the second side of that module to form a border pooling circuit for that module; and wherein the border pooling circuit of each module is connected by a first openable and closeable switch to an adjacent pooling circuit of an adjacent module in the same column and by a second openable and closeable switch to an adjacent pooling circuit of an adjacent module in the same row;

a memory pooling interface in each module connecting the memory in that module to the border pooling circuit of that module for enabling reading data from the memory of that module to the pooling circuit and for enabling writing data from the border pooling circuit to the memory.

2 . The data processing array of claim 1 , including a pooling row switch control line connected to each first switch in the column of modules for opening and closing all of the first switches in the column simultaneously, and a pooling column switch control line connected to each second switch in the row of modules for opening and closing all of the second switches in the row simultaneously.

3 . The data processing array of claim 2 , wherein each module comprises a light modulator, a modulation driver connected to the light modulator, and a modulation pooling interface connecting the modulation driver to the border pooling circuit of that module to enable writing data from the border pooling circuit to drive the light modulator.

4 . The data processing array of claim 3 , wherein each module comprises a light sensor and a sensor interface for placing data from the light sensor on the border pooling circuit.

5 . The data processing array of claim 1 , wherein each module comprises a data interface connecting an analog data line to the memory of the module for reading data from the memory to an analog to digital converter and for writing data from a digital to analog converter to the memory.

Continuity (5)
Continuation 16137522 · Sep 20, 2018
Provisional Application 62663465 · Apr 27, 2018
Provisional Application 62625711 · Feb 2, 2018
Provisional Application 62561061 · Sep 20, 2017
Related Publication 20230048377A1 · Feb 16, 2023
References Cited (5)
US 5392132A · Yamamoto et al. · 1995 [cited by applicant]
US 5963667A · Hashimoto et al. · 1999 [cited by applicant]
US 6529614B1 · Chao et al. · 2003 [cited by applicant]
US 20110137645A1 · Vary et al. · 2011 [cited by applicant]
US 20140147039A1 · Wang · 2014 [cited by examiner]