Dynamic rowhammer management with per-row hammer tracking

1 . A method for per-row hammer tracking in a DRAM device, comprising:

monitoring or detecting, by an activation command (ACT) detecting circuitry of the DRAM device, a number of row activation commands directed to each row of a bank of the DRAM device;

determining, by a next aggressor row circuitry of the DRAM device, a next aggressor row based on the number of row activation commands;

storing in a next aggressor row buffer coupled to the next aggressor circuitry a row to which the greatest number of row activation commands have been directed;

updating a current aggressor row buffer coupled to the next aggressor row buffer with the next aggressor row stored in the next aggressor row buffer based on detection of a refresh command by the refresh command detecting circuitry directed to the bank;

resetting a next aggressor count buffer coupled to the next-aggressor circuitry, following updating the current aggressor row buffer, the next aggressor count buffer storing a count of the number of row activation commands directed to the next aggressor row;

identifying by victim lookup circuitry one or more victim rows physically proximate to the current aggressor row and for populating a victim queue;

determining by victim queue circuitry coupled to the victim lookup circuitry based on detection of a refresh command directed to the bank, whether a victim queue is empty; and

refreshing a row in the victim queue with the victim queue circuitry based on detection of a refresh command directed to the bank and a determination the victim queue is not empty.

2 . The method of claim 1 , further comprising threshold determining circuitry coupled to the next aggressor row circuitry for:

determining an activation count threshold value based on a comparison of the number of row activation commands directed to the current aggressor row with at least one threshold value; and

providing the activation count threshold value to a memory controller.

3 . The method of claim 1 , further comprising threshold determining circuitry coupled to the next aggressor row circuitry for:

determining an activation count threshold value based on a comparison of the number of row activation commands directed to the rows in the one or more banks with at least one threshold value; and

providing the activation count threshold value to a memory controller.

4 . The method of claim 1 , further comprising threshold determining circuitry coupled to the next aggressor row circuitry for:

comparing, in response to a row activation command directed to a row, the number of row activation commands directed to the row with the number of row activation commands directed to the next aggressor row, wherein determining the next aggressor row comprises updating the next aggressor row with the row when the number of row activation commands directed to the row is greater than the number of row activation commands directed to the next aggressor row; and

resetting, in response to the row activation command directed to the row, a count of the number of row activation commands directed to the current aggressor row when the current aggressor row was updated with the next aggressor row after a refresh command preceding the row activation command directed to the row.

5 . The method of claim 4 , further comprising wherein the threshold determining circuitry is further configured for:

determining a number of rows in each of a plurality of buckets, including, for each bucket, counting a number of rows having a number of row activation commands directed thereto greater than or equal to a corresponding bucket activation count threshold of the bucket, wherein each bucket has a corresponding bucket activation count threshold different from all other buckets and a corresponding bucket threshold different from all other buckets;

selecting from among a subset of the buckets having non-zero numbers of rows therein, one of the buckets having a greatest bucket activation count threshold;

providing an activation count threshold value to a memory controller based on the bucket threshold of a selected one of the buckets; and

before resetting the count of the number of row activation commands directed to the current aggressor row, decrementing a row count of each bucket having the current aggressor row therein by the number of row activation commands directed to the current aggressor row.

6 . A system for per-row hammer tracking in a DRAM device, comprising:

aggressor processing circuitry comprising:

an activation command (ACT) detecting circuitry to monitor or detect a number of row activation commands directed to each row of a bank of the DRAM device;

a next aggressor row circuitry to determine a next aggressor row based on the number of row activation commands;

a next aggressor row buffer coupled to the next aggressor row circuitry storing a row to which the greatest number of row activation commands have been directed;

a next aggressor row count buffer coupled to the next aggressor row buffer storing

a number of activation commands directed to the row stored in the next aggressor row buffer;

mitigation processing circuitry comprising:

a current aggressor row buffer coupled to the next aggressor row buffer for storing a current aggressor row that is the row stored in the next aggressor row buffer;

a current aggressor count buffer coupled to the next aggressor row count buffer and storing the number of activation commands stored in the next aggressor count buffer;

refresh command detecting circuitry to detect a refresh command directed to the bank;

victim lookup circuitry coupled to the current aggressor row buffer to identify one or more victim rows physically proximate to the current aggressor row and for populating a victim queue;

victim queue circuitry coupled to the victim lookup circuitry and determining whether the victim queue is empty and configured to initiate refreshing a row in the victim queue based on detection of a refresh command directed to the bank and a determination the victim queue is not empty; and

wherein the mitigation processing circuitry is further configured to update a current aggressor row with the next aggressor row based on detection by the refresh command detecting circuitry of a refresh command directed to the bank.

7 . The system of claim 6 , wherein the aggressor processing circuitry is comprises threshold determining circuitry coupled to the next aggressor row circuitry configured to:

determine an activation count threshold value based on a comparison of the number of row activation commands directed to the current aggressor row with at least one threshold value; and

provide the activation count threshold value to a memory controller.

8 . The system of claim 6 , wherein the aggressor processing circuitry comprises threshold determining circuitry coupled to the next aggressor row circuitry configured to:

count a number of row activation commands directed to rows in one or more banks of the DRAM device;

determine an activation count threshold value based on a comparison of the number of row activation commands directed to the rows in the one or more banks with at least one threshold value; and

provide the activation count threshold value to a memory controller.

9 . The system of claim 6 , wherein the aggressor processing circuitry comprises threshold determining circuitry coupled to the next aggressor row circuitry configured to:

compare, in response to a row activation command directed to a row, the number of row activation commands directed to the row with the number of row activation commands directed to the next aggressor row, wherein the aggressor processing circuitry being configured to determine the next aggressor row includes being configured to update the next aggressor row with the row when the number of row activation commands directed to the row is greater than the number of row activation commands directed to the next aggressor row; and

reset, in response to the row activation command directed to the row, a count of the number of row activation commands directed to the current aggressor row when the current aggressor row was updated with the next aggressor row after a refresh command preceding the row activation command directed to the row.

10 . The system of claim 9 , wherein the aggressor processing circuitry comprises threshold determining circuitry coupled to the next aggressor row circuitry configured to:

determine a number of rows in each of a plurality of buckets, including, for each bucket, count a number of rows having a number of row activation commands directed thereto greater than or equal to a corresponding bucket activation count threshold of the bucket, wherein each bucket has a corresponding bucket activation count threshold different from all other buckets and a corresponding bucket threshold different from all other buckets;

select, from among a subset of the buckets having non-zero numbers of rows therein, one of the buckets having a greatest bucket activation count threshold;

provide an activation count threshold value to a memory controller based on the bucket threshold of a selected one of the buckets; and

before the count of the number of row activation commands directed to the current aggressor row is reset, decrement a row count of each bucket having the current aggressor row therein by the number of row activation commands directed to the current aggressor row.

11 . A dynamic random access memory (DRAM) device, comprising:

at least one data storage array comprising a plurality of rows;

refresh processing circuitry configured to direct refresh operations to the data storage array;

row hammering processing circuitry, comprising aggressor processing circuitry and mitigation processing circuitry;

wherein an activation command (ACT) detecting circuitry of the aggressor processing circuitry is configured to monitor or detect a number of row activation commands directed to each row of a bank of the DRAM device and a next aggressor row circuitry is configured to determine a next aggressor row based on the number of row activation commands;

a next aggressor row buffer is coupled to the next aggressor row circuitry and stores a row to which the greatest number of row activation commands have been directed;

a next aggressor row count buffer is coupled to the next aggressor row buffer storing a number of activation commands directed to the row stored in the next aggressor row buffer;

wherein the mitigation processing circuitry comprises:

a current aggressor row buffer storing the next aggressor row based on detection of a refresh command directed to the bank;

a current aggressor count buffer coupled to the next aggressor row count buffer and storing the number of activation commands stored in the next aggressor count buffer;

refresh command detecting circuitry to detect a refresh command directed to the bank;

victim lookup circuitry coupled to the current aggressor row buffer to identify one or more victim rows physically proximate to the current aggressor row and for populating a victim queue;

victim queue circuitry coupled to the victim lookup circuitry and determining whether the victim queue is empty and configured to initiate refreshing a row in the victim queue based on detection of a refresh command directed to the bank and a determination the victim queue is not empty; and

wherein the aggressor processing circuitry is further configured to reset the next aggressor row count buffer, following the updating of the current aggressor row, the next aggressor row count buffer's count of the number of row activation commands directed to the next aggressor row.

12 . The DRAM device of claim 11 , wherein the aggressor processing circuitry further comprises threshold determining circuitry coupled to the next aggressor row circuitry and configured to:

determine an activation count threshold value based on a comparison of the number of row activation commands directed to the current aggressor row with at least one threshold value; and

provide the activation count threshold value to a memory controller.

13 . The DRAM device of claim 11 , wherein the aggressor processing circuitry further comprises threshold determining circuitry coupled to the next aggressor row circuitry and configured to:

determine an activation count threshold value based on a comparison of the number of row activation commands directed to the rows in the one or more banks with at least one threshold value; and

provide the activation count threshold value to a memory controller.

14 . The DRAM device of claim 11 , wherein the aggressor processing circuitry further comprises threshold determining circuitry coupled to the next aggressor row circuitry and configured to:

compare, in response to a row activation command directed to a row, the number of row activation commands directed to the row with the number of row activation commands directed to the next aggressor row, wherein the aggressor processing circuitry being configured to determine the next aggressor row includes being configured to update the next aggressor row with the row when the number of row activation commands directed to the row is greater than the number of row activation commands directed to the next aggressor row; and

reset, in response to the row activation command directed to the row, a count of the number of row activation commands directed to the current aggressor row when the current aggressor row was updated with the next aggressor row after a refresh command preceding the row activation command directed to the row.