IP Library › Granted Patent US 12,494,402
Granted Patent B2
US 12,494,402 · App. 18/349,685 · Granted Dec 9, 2025

Semiconductor device

Inventor: Shinya Masuno (Nagaokakyo, JP)
Assignee: Murata Manufacturing Co., Ltd.
H01L23/295H01L23/5226
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Quick Facts
Patent No.
US 12,494,402
App. No.
18/349,685
Granted
Dec 9, 2025
Kind
B2
Abstract

A device layer contains a semiconductor element in part of a region thereof. An insulating layer is on one surface of the device layer. A support substrate including a semiconductor is on a surface of the insulating layer on an opposite side from a side where the device layer is disposed. The support substrate has an opening overlapping a semiconductor element region in which the semiconductor element is formed in plan view and extending from a bottom surface of the support substrate to the insulating layer, the bottom surface being on an opposite side from a side where the insulating layer is disposed. An insulating heat dissipation layer contacts the insulating layer in a region encompassed by the opening in plan view and has a thermal conductivity higher than that of the insulating layer.

Claims (24)

1 . A semiconductor device comprising:

a device layer including a semiconductor element in part of a region thereof;

an insulating layer on one surface of the device layer;

a support substrate including a semiconductor and disposed on a surface of the insulating layer located on an opposite side from a side where the device layer is disposed, the support substrate including an opening therein, the opening overlapping a semiconductor element region in which the semiconductor element is configured in plan view, and the opening extending from a bottom surface of the support substrate to the insulating layer, the bottom surface being on an opposite side from a side where the insulating layer is disposed; and

a heat dissipation layer that contacts the insulating layer in a region encompassed by the opening in plan view and has a thermal conductivity higher than a thermal conductivity of the insulating layer, and

at least part of a region including the bottom surface of the support substrate and a side surface of the opening is not covered by the heat dissipation layer.

2 . The semiconductor device according to claim 1 ,

wherein the support substrate includes Si.

3 . The semiconductor device according to claim 1 , wherein

the heat dissipation layer includes a resin including filler.

4 . The semiconductor device according to claim 1 , wherein

the semiconductor element region is encompassed by the opening in plan view.

5 . The semiconductor device according to claim 1 , wherein

no part of the bottom surface of the support substrate is covered by the heat dissipation layer.

6 . The semiconductor device according to claim 5 , wherein

at least part of a region of the side surface of the opening located on a side near the bottom surface is not covered by the heat dissipation layer.

7 . The semiconductor device according to claim 5 , wherein

the heat dissipation layer is spaced apart from the side surface of the opening.

8 . The semiconductor device according to claim 2 , wherein

the heat dissipation layer includes a resin including filler.

9 . The semiconductor device according to claim 2 , wherein

the semiconductor element region is encompassed by the opening in plan view.

10 . The semiconductor device according to claim 2 , wherein

no part of the bottom surface of the support substrate is covered by the heat dissipation layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2023
From: MASUNO, SHINYA
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 064557/0378 →
Priority Claims (1)
JP 2022-111157 · Jul 11, 2022 · national
Continuity (1)
Related Publication 20240014084A1 · Jan 11, 2024
References Cited (2)
US 9214337B2 · Carroll et al. · 2015 [cited by applicant]
US 10079160B1 · Margomenos · 2018 [cited by examiner]