Determining a locked status of a clock tracking circuit
An example apparatus includes a phase detector, a digital discriminator, and a logic circuit. A status signal of the phase detector is at least partially based on a phase relationship between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The digital discriminator may sample the status signal of the phase detector. The logic circuit may determine a locked status of the clock tracking circuit at least partially based on samples of the status signal of the phase detector.
1 . An apparatus, comprising:
a phase detector, wherein a status signal of the phase detector is at least partially based on a phase relationship between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock;
a digital discriminator to sample the status signal of the phase detector; and
a logic circuit to determine a locked status of the clock tracking circuit at least partially based on samples of the status signal of the phase detector.
2 . The apparatus of claim 1 , wherein the phase detector to set the status signal at least partially based on a phase threshold and the phase relationship between the reference clock and the feedback clock.
3 . The apparatus of claim 2 , wherein a value of the phase threshold is settable.
4 . The apparatus of claim 1 , wherein the phase detector to:
set the status signal to a first value at least partially responsive to determining that a determined amount of difference between the reference clock and the feedback clock is greater than a phase threshold.
5 . The apparatus of claim 4 , wherein the phase detector to:
set the status signal of the phase detector to a second value at least partially responsive to determining that a determined amount of difference between the reference clock and the feedback clock is equal to or less than a phase threshold, wherein the second value is different than a first value.
6 . The apparatus of claim 1 , wherein, to determine the locked status of the clock tracking circuit, the logic circuit to:
decode locked status information from samples of the status signal of a phase detector; and
determine the locked status of the clock tracking circuit at least partially based on the decoded locked status information.
7 . The apparatus of claim 1 , wherein the logic circuit to set a locked status signal to a first value to indicate a locked state and set the locked status signal to a second value to indicate a not locked state.
8 . The apparatus of claim 1 , wherein the phase detector to:
detect occurrences of like respective edges of the reference clock and the feedback clock; and
set the status signal to indicate whether or not the detected occurrences of like respective edges were within a predetermined range.
9 . The apparatus of claim 8 , wherein the phase detector to:
set the status signal to a first value responsive to a time difference between the detected occurrences of like respective edges of the reference clock and the feedback clock is less than a phase threshold.
10 . The apparatus of claim 9 , wherein the phase detector to:
set the status signal to a second value responsive to a time difference between the detected occurrences of like respective edges of the reference clock and the feedback clock is greater than or equal to a phase threshold, wherein the second value is different than the first value.
11 . The apparatus of claim 1 , wherein the digital discriminator includes a decimator to decimate values of the status signal.
12 . The apparatus of claim 1 , wherein the digital discriminator includes an interpolator to interpolate values based on the status signal.
13 . The apparatus of claim 1 , wherein the digital discriminator includes a digital filter to block status signal that is indicative of transient phase error and pass status signal that is indicative of steady-state phase error.
14 . A method, comprising:
setting a status signal of a phase detector, wherein the status signal of the phase detector is set at least partially based on a phase relationship between a reference clock and a feedback clock generated by a clock tracking circuit to track the reference clock, the phase relationship between the reference clock and the feedback clock being at least partially based on a relationship between a phase threshold and an amount of difference between the reference clock and the feedback clock; and
generating a signal indicative of a locked status of the clock tracking circuit at least partially based on the status signal of the phase detector.
15 . The method of claim 14 , comprising:
determining whether or not the phase relationship between the reference clock and the feedback clock falls within a predetermined range; and
setting the status signal of the phase detector at least partially based on the determination.
16 . The method of claim 14 , comprising:
setting the status signal of the phase detector to a value at least partially responsive to determining that a determined amount of difference between the reference clock and the feedback clock is greater than the phase threshold.
17 . The method of claim 14 , comprising:
setting the status signal of the phase detector to a value at least partially responsive to determining that a determined amount of difference between the reference clock and the feedback clock is equal to or less than the phase threshold.
18 . The method of claim 14 ,
obtaining samples of the status signal of the phase detector;
decoding locked status information from samples of the status signal of the phase detector; and
determining the locked status of the clock tracking circuit at least partially based on the decoded locked status information.
19 . A method, comprising:
detecting occurrences of like respective edges of a reference clock and a feedback clock generated by a clock tracking circuit to track the reference clock;
setting a status signal of a phase detector to indicate whether or not the detected occurrences of like respective edges were within a predetermined range; and
generating a signal indicative of a locked status of the clock tracking circuit at least partially based on the status signal of the phase detector.
20 . The method of claim 19 , wherein setting the status signal to indicate whether or not the detected occurrences of like respective edges were within the predetermined range comprises:
setting the status signal to a value responsive to a time difference between the detected occurrences of like respective edges of the reference clock and the feedback clock being less than a phase threshold.
21 . The method of claim 19 , wherein setting the status signal to indicate whether or not the detected occurrences of like respective edges were within the predetermined range comprises:
setting the status signal to a value responsive to a time difference between the detected occurrences of like respective edges of the reference clock and the feedback clock being greater than or equal to a phase threshold.