IP Library › Granted Patent US 12,494,800
Granted Patent B2
US 12,494,800 · App. 17/559,989 · Granted Dec 9, 2025

Apparatus and method for constant detection during compress operations

Inventors: James David Guilford (Northborough, MA); Vinodh Gopal (Westborough, MA); Daniel Frederick Cutter (Maynard, MA); Kirk Yap (Westborough, MA)
Assignee: Intel Corporation
H03M7/3084G06F3/0608G06F3/0641G06F3/0679
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Quick Facts
Patent No.
US 12,494,800
App. No.
17/559,989
Granted
Dec 9, 2025
Kind
B2
Abstract

Apparatus and method for detecting a constant data block are described herein. An apparatus embodiment includes compression circuitry to perform compression operations on a memory block; constant detection circuitry to, concurrently with performance of the compression operations on the memory block, determine that the memory block is a constant data block comprised of only repeat instances of a constant value; and controller circuitry to associate a first indication with the memory block based on the determination, the first indication usable for controlling whether to abort the compression operations or whether to discard a compressed memory block generated from the compression operations.

Claims (38)

1 . An apparatus comprising:

compression circuitry to perform compression operations on a memory block;

constant detection circuitry to, concurrently with performance of the compression operations on the memory block, perform constant check operations that comprise a determination of whether the memory block is a constant data block comprised of only repeat instances of a constant value; and

controller circuitry to associate a first indication with the memory block based on the determination that the memory block is a constant data block, wherein the first indication is usable for controlling whether to abort the compression operations or whether to discard a compressed memory block generated from the compression operations.

2 . The apparatus of claim 1 , wherein the controller circuitry is to associate the first indication with the memory block by associating the first indication with a memory address of the memory block.

3 . The apparatus of claim 1 , further comprising:

fill circuitry to, responsive to a request for the memory block, generate a copy of the memory block using the constant value when the memory block is associated with the first indication.

4 . The apparatus of claim 3 , further comprising:

decompression circuitry to, responsive to the request for the memory block, generate the copy of the memory block by decompressing the compressed memory block when the memory block is not associated with the first indication.

5 . The apparatus of claim 1 , wherein the compression operations comprise at least a first operation to analyze the memory block to generate compression parameters and a second operation to generate the memory block based on the compression parameters.

6 . The apparatus of claim 5 , wherein the compression circuitry is to abort the second operation responsive to the determination that the memory block is a constant data block.

7 . The apparatus of claim 1 , further comprising:

storage unit to store the compressed memory block, the storage unit comprising a system memory or a cache.

8 . The apparatus of claim 1 , wherein the memory block comprises a memory page.

9 . The apparatus of claim 1 , wherein the memory block comprises M bits, the constant value comprises N bit, and the memory block comprises M/N occurrences of the constant value.

10 . The apparatus of claim 9 , wherein N comprises one of 8, 16, and 32.

11 . The apparatus of claim 1 , wherein the compression operations is performed based on a DEFLATE or a Lempel-Ziv-Oberhumer (LZO) compression scheme.

12 . The apparatus of claim 1 , wherein the determination that the memory block is a constant data block further comprises dividing the memory block into a plurality of smaller memory blocks and determining that each of the plurality of smaller memory blocks is also comprised of only repeat instances of the constant value.

13 . The apparatus of claim 12 , wherein the constant value is stored in a state structure and compared with values in each of the plurality of smaller memory blocks.

14 . A method comprising:

performing compression operations on a memory block;

performing constant check operations that comprise a determination of whether the memory block is a constant data block comprised of only repeat instances of a constant value, wherein the constant check operations are performed concurrently with the compression operations on the memory block; and

associating a first indication with the memory block based on the determination that the memory block is a constant data block, wherein the first indication is usable for controlling whether to abort the compression operations or whether to discard a compressed memory block generated from the compression operations.

15 . The method of claim 14 , wherein associating the first indication with the memory block further comprises associating the first indication with a memory address of the memory block.

16 . The method of claim 14 , further comprises:

responsive to a request for the memory block, generating a copy of the memory block using the constant value when the memory block is associated with the first indication.

17 . The method of claim 16 , further comprises:

responsive to the request for the memory block, generating the copy of the memory block by decompressing the compressed memory block when the memory block is not associated with the first indication.

18 . The method of claim 14 , wherein the compression operations comprise at least a first operation to analyze the memory block to generate compression parameters and a second operation to generate the memory block based on the compression parameters.

19 . The method of claim 18 , further comprises:

aborting the second operation responsive to the determination that the memory block is a constant data block.

20 . The method of claim 14 , further comprises:

storing the compressed memory block in a storage unit, the storage unit comprising a system memory or a cache.

21 . The method of claim 14 , wherein the memory block comprises a memory page.

22 . The method of claim 14 , wherein the memory block comprises M bits, the constant value comprises N bit, and the memory block comprises M/N occurrences of the constant value.

23 . The method of claim 22 , wherein N comprises one of 8, 16, and 32.

24 . The method of claim 14 , wherein the compression operations is performed based on a DEFLATE or a Lempel-Ziv-Oberhumer (LZO) compression scheme.

25 . The method of claim 14 , wherein determining that the memory block is a constant data block further comprises dividing the memory block into a plurality of smaller memory blocks and determining that each of the plurality of smaller memory blocks is also comprised of only repeat instances of the constant value.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2022
From: GUILFORD, JAMES DAVID; GOPAL, VINODH; CUTTER, DANIEL FREDERICK; YAP, KIRK
To: INTEL CORPORATION
Reel/Frame 059080/0322 →
Continuity (1)
Related Publication 20230198548A1 · Jun 22, 2023
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