IP Library › Granted Patent US 12,495,657
Granted Patent B1
US 12,495,657 · App. 18/063,923 · Granted Dec 9, 2025

Micro-LED with field-effect isolation

Inventors: Andrea Pinos (Plymouth, GB); Wei Sin Tan (Plymouth, GB); Samir Mezouari (Swindon, GB); Sean Denis Connor (Swindon, GB)
Assignee: Meta Platforms Technologies, LLC
H10H29/142H01L25/18
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Quick Facts
Patent No.
US 12,495,657
App. No.
18/063,923
Granted
Dec 9, 2025
Kind
B1
Abstract

A micro-light emitting diode (micro-LED) device includes a plurality of semiconductor epitaxial layers that includes a quantum well layer configured to emit light. The micro-LED device also includes an array of electrodes for an array of micro-LEDs, the array of electrodes coupled to the plurality of semiconductor epitaxial layers. The micro-LED device further includes an insulator grid coupled to the plurality of semiconductor epitaxial layers and positioned in regions between individual electrodes of the array of electrodes, and a gate grid coupled to the insulator grid and configured to apply an electric field through the insulator grid to the plurality of semiconductor epitaxial layers in the regions between the individual electrodes of the array of electrodes to electrically isolate the plurality of semiconductor epitaxial layers into individual micro-LEDs of the array of micro-LEDs.

Claims (49)

1 . A micro-light emitting diode (micro-LED) device comprising:

a plurality of semiconductor epitaxial layers, the plurality of semiconductor epitaxial layers including a quantum well layer configured to emit light;

an array of electrodes for an array of micro-LEDs, the array of electrodes coupled to the plurality of semiconductor epitaxial layers;

an insulator grid coupled to the plurality of semiconductor epitaxial layers and positioned in regions between individual electrodes of the array of electrodes; and

a gate grid coupled to the insulator grid and configured to apply an electric field through the insulator grid to the plurality of semiconductor epitaxial layers in the regions between the individual electrodes of the array of electrodes to electrically isolate the plurality of semiconductor epitaxial layers into individual micro-LEDs of the array of micro-LEDs,

wherein the gate grid is configured to apply the electric field to accumulate electrons in regions of the quantum well layer that are aligned with the gate grid.

2 . The micro-LED device of claim 1 , wherein:

the plurality of semiconductor epitaxial layers includes a cladding layer between the quantum well layer and the insulator grid and between the quantum well layer and the array of electrodes; and

the gate grid is configured to apply the electric field to deplete holes in the cladding layer between the quantum well layer and the insulator grid.

3 . The micro-LED device of claim 2 , wherein the cladding layer is thinner in regions between the quantum well layer and the insulator grid than in regions between the quantum well layer and the array of electrodes.

4 . The micro-LED device of claim 3 , wherein the cladding layer between the quantum well layer and the array of electrodes includes an etch-stop layer embedded in the cladding layer.

5 . The micro-LED device of claim 4 , wherein the etch-stop layer includes AIAs.

6 . The micro-LED device of claim 2 , wherein:

the plurality of semiconductor epitaxial layers includes at least two quantum barrier layers that sandwich the quantum well layer; and

the cladding layer is characterized by an energy bandgap wider than energy bandgaps of the at least two quantum barrier layers.

7 . The micro-LED device of claim 6 , wherein the cladding layer includes AlGaInP.

8 . The micro-LED device of claim 1 , wherein the array of electrodes includes an array of anodes for the array of micro-LEDs.

9 . The micro-LED device of claim 8 , further comprising a common cathode for the array of micro-LEDs.

10 . The micro-LED device of claim 1 , wherein each electrode of the array of electrodes includes:

a transparent conductive oxide layer coupled to the plurality of semiconductor epitaxial layers; and

a metal layer coupled to the transparent conductive oxide layer.

11 . The micro-LED device of claim 1 , wherein the gate grid is electrically shorted to an electrode of the array of electrodes for a micro-LED of the array of micro-LEDs.

12 . The micro-LED device of claim 1 , further comprising a backplane bonded to the array of electrodes, the backplane including drive circuits for driving the array of micro-LEDs.

13 . The micro-LED device of claim 1 , further comprising an array of micro-lenses on a side of the plurality of semiconductor epitaxial layers opposing the array of electrodes.

14 . The micro-LED device of claim 1 , wherein each electrode of the array of electrodes includes:

a transparent conductive oxide layer coupled to the plurality of semiconductor epitaxial layers;

a first distributed Bragg reflector (DBR) structure coupled to the transparent conductive oxide layer;

a metal layer coupled to the first DBR structure; and

a through-via in the first DBR structure, the through-via electrically coupling the metal layer to the transparent conductive oxide layer.

15 . The micro-LED device of claim 14 , further comprising a second DBR structure, wherein the first DBR structure and the second DBR structure are on opposite sides of the plurality of semiconductor epitaxial layers to form a resonant cavity.

16 . The micro-LED device of claim 1 , wherein the gate grid includes a transparent conductive oxide layer coupled to the insulator grid.

17 . The micro-LED device of claim 16 , wherein the gate grid further includes a metal layer electrically coupled to the transparent conductive oxide layer.

18 . The micro-LED device of claim 17 , wherein the gate grid further includes:

a DBR structure coupled to the transparent conductive oxide layer; and

a through-via in the DBR structure, the through-via electrically coupling the metal layer to the transparent conductive oxide layer.

19 . A micro-light emitting diode (micro-LED) device comprising:

a plurality of semiconductor epitaxial layers, the plurality of semiconductor epitaxial layers including a quantum well layer configured to emit light;

an array of electrodes for an array of micro-LEDs, the array of electrodes coupled to the plurality of semiconductor epitaxial layers;

an insulator grid coupled to the plurality of semiconductor epitaxial layers and positioned in regions between individual electrodes of the array of electrodes; and

a gate grid coupled to the insulator grid and configured to apply an electric field through the insulator grid to the plurality of semiconductor epitaxial layers in the regions between the individual electrodes of the array of electrodes to electrically isolate the plurality of semiconductor epitaxial layers into individual micro-LEDs of the array of micro-LEDs,

wherein:

the plurality of semiconductor epitaxial layers includes a cladding layer between the quantum well layer and the insulator grid and between the quantum well layer and the array of electrodes; and

the gate grid is configured to apply the electric field to deplete holes in the cladding layer between the quantum well layer and the insulator grid.

20 . A micro-light emitting diode (micro-LED) device comprising:

a plurality of semiconductor epitaxial layers, the plurality of semiconductor epitaxial layers including a quantum well layer configured to emit light;

an array of electrodes for an array of micro-LEDs, the array of electrodes coupled to the plurality of semiconductor epitaxial layers;

an insulator grid coupled to the plurality of semiconductor epitaxial layers and positioned in regions between individual electrodes of the array of electrodes; and

a gate grid coupled to the insulator grid and configured to apply an electric field through the insulator grid to the plurality of semiconductor epitaxial layers in the regions between the individual electrodes of the array of electrodes to electrically isolate the plurality of semiconductor epitaxial layers into individual micro-LEDs of the array of micro-LEDs,

wherein the plurality of semiconductor epitaxial layers includes a cladding layer between the quantum well layer and the array of electrodes but not between the quantum well layer and the insulator grid.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2023
From: PINOS, ANDREA; TAN, WEI SIN; MEZOUARI, SAMIR; CONNOR, SEAN DENIS
To: META PLATFORMS TECHNOLOGIES, LLC
Reel/Frame 062274/0522 →
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