IP Library › Granted Patent US 12,498,859
Granted Patent B2
US 12,498,859 · App. 18/130,734 · Granted Dec 16, 2025

Systems and method for tracking activations to perform row hammer mitigation in memory modules

Inventor: Moinuddin Qureshi (Atlanta, GA)
Assignee: Georgia Tech Research Corporation
G06F3/0614G06F3/0673G06F21/00G06F21/50
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Quick Facts
Patent No.
US 12,498,859
App. No.
18/130,734
Granted
Dec 16, 2025
Kind
B2
Abstract

A hybrid tracker system and method are disclosed for RH mitigation, which combines the best of both SRAM and DRAM to enable low-cost mitigation of RH at ultra-low thresholds. The system consists of two structures. First, an SRAM-based structure is provided that tracks aggregated counts at the granularity of a group of rows and is sufficient for the vast majority of rows, which receive only a few activations. Second, a per-row tracker stored in the DRAM-array is provided which can track an arbitrary number of rows; however, to limit performance overheads, this tracker is used only for the small number of rows that exceed the tracking capability of the SRAM-based structure.

Claims (55)

1 . A method for Row-hammer mitigation comprising:

determining that a row of a plurality of rows of a DRAM module has been activated, wherein the DRAM module is part of a memory device comprising the DRAM module and an SRAM module; and

in response to the determination that the row has been activated:

determining a group of rows of a plurality of groups of rows that includes the row that has been activated, wherein each group of rows includes a unique subset of rows of the plurality of rows and each row of the plurality of rows is included in a group of rows of the plurality of groups of rows;

determining that a count associated with the group of rows in a group-count table satisfies a group-count threshold, wherein the group-count table is stored in the SRAM module and not in the DRAM module, and wherein the group-count table includes a different count for each group of rows of the plurality of rows;

in response to determining that the count associated with the group of rows satisfies the group-count threshold:

incrementing a count associated with an entry for the row in a row-count table, wherein the row-count table is stored in the DRAM module and not in the SRAM module;

determining that the count associated with the entry for the row in the row-count table satisfies a row-count threshold; and

in response to the determination that the count associated with the entry for the row in the row-count table satisfies the row-count threshold, performing row hammer mitigation.

2 . The method of claim 1 , further comprising:

determining that the count associated with the group of rows in the group-count table does not satisfy the group-count threshold; and

in response to the determination that the count associated with the group of rows in the group-count table does not satisfy the group-count threshold, increment the count associated with the group of rows in the group-count table.

3 . The method of claim 1 , further comprising:

after performing the row hammer mitigation, setting the count associated with the entry for the row that has been activated to zero.

4 . The method of claim 1 , wherein the count associated with the group of rows in the group-count table satisfies the group-count threshold when the count is equal to the group-count threshold.

5 . The method of claim 1 , wherein the count associated with the entry for the row satisfies the row-count threshold when the count is equal to the row-count threshold.

6 . The method of claim 1 , wherein each row of the plurality of rows is only in one group of rows of the plurality of groups of rows.

7 . The method of claim 1 , further comprising maintaining a row-count cache of the row-count table.

8 . The method of claim 7 , wherein the row count cache is maintained in the SRAM module.

9 . The method of claim 1 , wherein the method is performed by a memory controller of the memory device.

10 . A memory device comprising:

a memory controller;

an SRAM module; and

a DRAM module comprising a plurality of rows, wherein the memory controller is adapted to:

determine that a row of the plurality of rows of the DRAM module has been activated; and

in response to the determination that the row has been activated:

determine a group of rows of a plurality of groups of rows that includes the row that has been activated, wherein each group of rows includes a unique subset of rows of the plurality of rows and each row of the plurality of rows is included in a group of rows of the plurality of groups of rows;

determine that a count associated with the group of rows in a group-count table satisfies a group-count threshold, wherein the group-count table is stored in the SRAM module and not in the DRAM module, and wherein the group-count table includes a different count for each group of rows of the plurality of rows;

in response to determining that the count associated with the group of rows satisfies the group-count threshold:

increment a count associated with an entry for the row in a row-count table, wherein the row-count table is stored in the DRAM module and not in the SRAM module;

determine that the count associated with the entry for the row in the row-count table satisfies a row-count threshold; and

in response to the determination that the count associated with the entry for the row in the row-count table satisfies the row-count threshold, perform row hammer mitigation.

11 . The memory device of claim 10 , wherein the memory device is further adapted to:

determine that the count associated with the group of rows in the group-count table does not satisfy the group-count threshold; and

in response to the determination that the count associated with the group of rows in the group-count table does not satisfy the group-count threshold, increment the count associated with the group of rows in the group-count table.

12 . The memory device of claim 10 , wherein the memory device is further adapted to:

after performing the row hammer mitigation, set the count associated with the entry for the row that has been activated to zero.

13 . The memory device of claim 10 , wherein the count associated with the group of rows in the group-count table satisfies the group-count threshold when the count is equal to the group-count threshold.

14 . The memory device of claim 10 , wherein the count associated with the entry for the row satisfies the row-count threshold when it is equal to the row-count threshold.

15 . The memory device of claim 10 , further comprising maintaining a row-count cache of the row-count table.

16 . A memory device comprising:

a memory controller;

an SRAM module; and

a DRAM module comprising a plurality of rows, wherein the memory controller is adapted to:

determine that a row of the plurality of rows of the DRAM module has been activated; and

in response to the determination that the row has been activated:

determine a group of rows of a plurality of groups of rows that includes the row that has been activated, wherein each group of rows includes a unique subset of rows of the plurality of rows and each row of the plurality of rows is included in a group of rows of the plurality of groups of rows;

determine whether a count associated with the group of rows in a group-count table is less than a group-count threshold, wherein the group-count table is stored in the SRAM module and not in the DRAM module;

if it is not determined that the count associated with the group of rows is less than the group-count threshold:

increment a count associated with an entry for the row in a row-count table, wherein the row-count table is stored in the DRAM module and not in the SRAM module;

determine that the count associated with the entry for the row in the row-count table is not less than a row-count threshold; and

in response to the determination that the count associated with the entry for the row in the row-count table is not less than the row-count threshold, perform row hammer mitigation; and

after performing the row hammer mitigation, set the count associated with the entry for the row that has been activated to zero;

if it is determined that the count associated with the group of rows is less than the group-count threshold:

increment the count associated with the group of rows in the group-count table.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2025
From: QURESHI, MOINUDDIN
To: GEORGIA TECH RESEARCH CORPORATION
Reel/Frame 072942/0323 →
Continuity (2)
Provisional Application 63327518 · Apr 5, 2022
Related Publication 20230315299A1 · Oct 5, 2023
References Cited (33)
US 20140006704A1 · Greenfield · 2014 [cited by examiner]
US 20190066808A1 · Nale · 2019 [cited by examiner]
US 20210065775A1 · Hush · 2021 [cited by examiner]
“Spec cpu2017 benchmark suite,” in Standard Performance Evaluation Corporation. [Online]. Available: http://www.spec.org/cpu2017/. [cited by applicant]
“half-double”: Next-row-over assisted rowhammer. https://github.com/google/hammer-kit/blob/main/20210525_half_double.pdf. [cited by applicant]
Aweke, Z. B. et al., “Anvil:Software-based protection against next-generation rowhammer attacks,” ACM SIGPLAN Notices, vol. 51, No. 4, pp. 743-755, 2016. [cited by applicant]
Bennett, T. et al., “Panopticon: A complete in-dram rowhammer mitigation,” in Workshop on DRAM Security (DRAMSec), 2021. [cited by applicant]
Bienia, C. et al., “The parsec benchmark suite: Characterization and architectural implications,” in Proceedings of the 17th international conference on Parallel architectures and compilation techniques, 2008, pp. 72-81. [cited by applicant]
Chatterjee, N. et al., “Usimm: the utah simulated memory module,” University of Utah, Tech. Rep, 2012. [cited by applicant]
Cojocar, L. et al., “Exploiting correcting codes: On the effectiveness of ecc memory against rowhammer attacks,” in 2019 IEEE Symposium on Security and Privacy (SP). IEEE, 2019, pp. 55-71. [cited by applicant]
Costan, V. and Devadas, S., “Intel sgx explained.” IACR Cryptol. ePrint Arch., vol. 2016, No. 86, pp. 1-118, 2016. [cited by applicant]
Frigo, P. et al., “TRRespass: Exploiting the many sides of target row refresh,” in 2020 IEEE Symposium on Security and Privacy (SP). IEEE, 2020, pp. 747-762. [cited by applicant]
Gruss, D. et al., “Another flip in the wall of rowhammer defenses,” in 2018 IEEE Symposium on Security and Privacy (SP). IEEE, 2018, pp. 245-261. [cited by applicant]
Gruss, D., Maurice, C. and Mangard, S. “Rowhammer. js: A remote software-induced fault attack in javascript,” in International conference on detection of intrusions and malware, and vulnerability assessment. Springer, 2… [cited by applicant]
Jang, Y. et al., “Sgx-bomb: Locking down the processor via rowhammer attack,” in Proceedings of the 2nd Workshop on System Software for Trusted Execution, 2017, pp. 1-6. [cited by applicant]
JEDEC Standard, “DDR4 SDRAM Standard JESD79-4B.” [cited by applicant]
Kim, D.-H. et al., “Architectural support for mitigating row hammering in dram memories,” IEEE CAL, vol. 14, No. 1, pp. 9-12, 2014. [cited by applicant]
Kim, J.S. et al., “Revisiting rowhammer: An experimental analysis of modern dram devices and mitigation techniques,” in 2020 ACM/IEEE 47th ISCA. IEEE, 2020, pp. 638-651. [cited by applicant]
Kim, M. J. et al., “Mithril: Cooperative row hammer protection on commodity dram leveraging managed refresh,” arXiv preprint arXiv:2108.06703, 2021. [cited by applicant]
Kim, Y. et al., “Flipping bits in memory without accessing them: An experimental study of dram disturbance errors,” ACM SIGARCH Computer Architecture News, vol. 42, No. 3, pp. 361-372, 2014. [cited by applicant]
Kwong, A. et al., “Rambleed: Reading bits in memory without accessing them,” in 2020 IEEE Symposium on Security and Privacy (SP). IEEE, 2020, pp. 695-711. [cited by applicant]
Lee, E. et al., “Twice: preventing row-hammering by exploiting time window counters,” in Proceedings of the 46th International Symposium on Computer Architecture, 2019, pp. 385-396. [cited by applicant]
Micron. Ddr4 sdram datasheet. https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr4/8gb_ddr4_sdram.pdf. [cited by applicant]
Muralimanohar, N., Balasubramonian, R. and Jouppi, N.P. “Cacti 6.0: A tool to model large caches,” HP laboratories, vol. 27, 2009. [cited by applicant]
Park, Y. et al., “Graphene: Strong yet Lightweight Row Hammer Protection,” in 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (Micro). Athens, Greece: IEEE, Oct. 2020, pp. 1-13. [Online]. Availabl… [cited by applicant]
Beamer, K. A. S. and Patterson, D. “The gap benchmark suite,” in arXiv preprint arXiv:1508.03619, 2015. [cited by applicant]
Seaborn, M. and Dullien, T., “Exploiting the dram rowhammer bug to gain kernel privileges,” Black Hat, vol. 15, p. 71, 2015. [cited by applicant]
Seyedzadeh, S. M., et al., “Mitigating wordline crosstalk using adaptive trees of counters,” in 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2018, pp. 612-623. [cited by applicant]
Son, M. et al., “Making dram stronger against row hammering,” in Proceedings of the 54th Annual Design Automation Conference 2017, 2017, pp. 1-6. [cited by applicant]
Van Der Veen, V. et al., “Drammer: Deterministic rowhammer attacks on mobile platforms,” in Proceedings of the 2016 ACM SIGSAC conference on computer and communications security, 2016, pp. 1675-1689. [cited by applicant]
Yaglikci, A. G. et al., “Blockhammer: Preventing rowhammer at low cost by blacklisting rapidly accessed dram rows,” in 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, 2021, pp. … [cited by applicant]
You, J. M. and Yang, J.-S. “Mrloc: Mitigating row-hammering based on memory locality,” in 2019 56th ACM/IEEE Design Automation Conference (DAC). IEEE, 2019, pp. 1-6. [cited by applicant]
Zhang, Z. et al., “Pthammer: Cross-userkernel-boundary rowhammer through implicit accesses,” in 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (Micro). IEEE, 2020, pp. 28-41. [cited by applicant]