Packaging architecture with intermediate routing layers
Embodiments of the present disclosure provide a microelectronic assembly comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third layer between the first layer and the second layer, the third layer comprising conductive routing traces in a dielectric. A first interface is between the first layer and the third layer and includes first interconnects having a first pitch of less than 10 micrometers between adjacent ones of the first interconnects, a second interface is between the second layer and the third layer and includes second interconnects having a second pitch of less than 10 micrometers between adjacent ones of the second interconnects, and the routing traces in the third layer are to provide lateral electrical coupling between the first interconnects and the second interconnects.
1 . A microelectronic assembly, comprising:
a first plurality of integrated circuit (IC) dies in a first layer;
a second plurality of IC dies in a second layer; and
a third layer between the first layer and the second layer, the third layer comprising conductive routing traces and conductive vias in a dielectric,
wherein:
a first interface is between the first layer and the third layer and includes first interconnects between conductive contacts of the first layer and a first portion of the conductive vias of the third layer, the first interconnects having a first pitch of less than 10 micrometers between adjacent ones of the first interconnects,
a second interface is between the second layer and the third layer and includes second interconnects between conductive contacts of the second layer and a second portion of the conductive vias of the third layer, the second interconnects having a second pitch of less than 10 micrometers between adjacent ones of the second interconnects, and
the routing traces in the third layer are to provide lateral electrical coupling between the first interconnects and the second interconnects.
2 . The microelectronic assembly of claim 1 , wherein:
the dielectric comprises a first dielectric, and
the second layer comprises a second dielectric with through-dielectric vias (TDVs) in the second dielectric.
3 . The microelectronic assembly of claim 1 , wherein the dielectric comprises a compound of silicon and at least one of oxygen, carbon, and nitrogen.
4 . The microelectronic assembly of claim 1 , wherein the third layer further comprises passive components.
5 . The microelectronic assembly of claim 1 , wherein the third layer further comprises at least one of a diode and a transistor.
6 . The microelectronic assembly of claim 1 , wherein the third layer comprises a plurality of dielectric layers and metal layers, and a third portion of the conductive vias electrically couple the metal layers.
7 . An IC package, comprising:
a first IC die having a first conductive contact in a first layer;
a second IC die having a second conductive contact in a second layer;
a routing layer comprising a dielectric and a routing trace, a first via, and a second via in the dielectric, the routing layer being between the first IC die and the second IC die to electrically couple the first IC die and the second IC die, wherein the first conductive contact is bonded to the first via at a first interconnect and the second conductive contact is bonded to the second via at a second interconnect, and the dielectric comprises an inorganic material; and
a package substrate.
8 . The IC package of claim 7 , wherein:
the dielectric is a first dielectric,
the routing trace is a first routing trace, and
the IC package further comprises:
a second dielectric in the first layer;
a TDV in the second dielectric; and
a second routing trace in the routing layer, to electrically couple the TDV and the second IC die.
9 . The IC package of claim 8 , wherein a distance between the first routing trace and the second routing trace is less than 10 micrometers.
10 . The IC package of claim 7 , wherein:
the dielectric is a first dielectric,
the routing trace is a first routing trace, and
the IC package further comprises:
a second dielectric in the first layer and the second layer;
a first TDV in the second dielectric of the first layer;
a second TDV in the second dielectric of the second layer; and
a second routing trace in the routing layer, to electrically couple the first TDV and the second TDV.
11 . The IC package of claim 7 , wherein the first interconnect and the second interconnect comprise die-to-die (DTD) interconnects having a pitch of less than 10 micrometers.
12 . The IC package of claim 7 , wherein the package substrate is coupled to one of the first layer and the second layer.
13 . The IC package of claim 12 , wherein the package substrate is coupled with die-to-package-substrate (DTPS) interconnects having another pitch greater than 10 micrometers.
14 . The IC package of claim 7 , wherein:
the IC package is a first IC package,
the first IC die is located at a first location in the first IC package,
the routing trace is a first routing trace between the first interconnect at the first location and the second interconnect at a second location, and
a second IC package is substantially identical to the first IC package in components and arrangement of the components except in following differences:
the first IC die is located at a third location in the first IC package,
the routing trace in the second IC package is a second routing trace, and
the second routing trace is between the first interconnect at the third location and the second interconnect at the second location.
15 . The IC package of claim 7 , wherein the dielectric comprises a compound of silicon and at least one of oxygen, carbon, and nitrogen.
16 . The IC package of claim 7 , wherein the routing layer further comprises at least one of: a transformer, an inductor, a capacitor, a resistor, a diode and a transistor.