Integrated circuit structures with backside self-aligned penetrating conductive source or drain contact
Integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and extends into the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.
1 . An integrated circuit structure, comprising:
a sub-fin structure over a vertical stack of horizontal nanowires;
an epitaxial source or drain structure laterally adjacent and coupled to the vertical stack of horizontal nanowires; and
a conductive source or drain contact laterally adjacent to the sub-fin structure and extending into the epitaxial source or drain structure, wherein the conductive source or drain contact does not extend around the epitaxial source or drain structure, and wherein the conductive source or drain contact is laterally adjacent to a nanowire of the vertical stack of horizontal nanowires.
2 . The integrated circuit structure of claim 1 , further comprising a gate structure around the vertical stack of horizontal nanowires and below the sub-fin structure.
3 . The integrated circuit structure of claim 1 , further comprising a dielectric layer over the sub-fin structure and over the conductive source or drain contact.
4 . The integrated circuit structure of claim 3 , further comprising a conductive line or via in the dielectric layer, the conductive line or via coupled to the conductive source or drain contact.
5 . The integrated circuit structure of claim 1 , wherein an uppermost surface of the sub-fin structure is co-planar with an uppermost surface of the conductive source or drain contact.
6 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a sub-fin structure over a vertical stack of horizontal nanowires;
an epitaxial source or drain structure laterally adjacent and coupled to the vertical stack of horizontal nanowires; and
a conductive source or drain contact laterally adjacent to the sub-fin structure and extending into the epitaxial source or drain structure, wherein the conductive source or drain contact does not extend around the epitaxial source or drain structure, and wherein the conductive source or drain contact is laterally adjacent to a nanowire of the vertical stack of horizontal nanowires.
7 . The computing device of claim 6 , further comprising:
a memory coupled to the board.
8 . The computing device of claim 6 , further comprising:
a communication chip coupled to the board.
9 . The computing device of claim 6 , wherein the component is a packaged integrated circuit die.
10 . The computing device of claim 6 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
11 . An integrated circuit structure, comprising:
a sub-fin structure over a fin;
an epitaxial source or drain structure laterally adjacent and coupled to the fin; and
a conductive source or drain contact laterally adjacent to the sub-fin structure and extending into the epitaxial source or drain structure, wherein the conductive source or drain contact does not extend around the epitaxial source or drain structure, and wherein the conductive source or drain contact is laterally adjacent to the fin.
12 . The integrated circuit structure of claim 11 , further comprising a gate structure around the fin and below the sub-fin structure.
13 . The integrated circuit structure of claim 11 , further comprising a dielectric layer over the sub-fin structure and over the conductive source or drain contact.
14 . The integrated circuit structure of claim 13 , further comprising a conductive line or via in the dielectric layer, the conductive line or via coupled to the conductive source or drain contact.
15 . The integrated circuit structure of claim 11 , wherein an uppermost surface of the sub-fin structure is co-planar with an uppermost surface of the conductive source or drain contact.
16 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a sub-fin structure over a fin;
an epitaxial source or drain structure laterally adjacent and coupled to the fin; and
a conductive source or drain contact laterally adjacent to the sub-fin structure and extending into the epitaxial source or drain structure, wherein the conductive source or drain contact does not extend around the epitaxial source or drain structure, and wherein the conductive source or drain contact is laterally adjacent to the fin.
17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.
18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.
20 . The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.