Semiconductor device with capping layer
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a capping mask layer positioned on the substrate; a first gate insulating layer positioned along the capping mask layer, inwardly positioned in the substrate, and including a U-shaped cross-sectional profile; a first work function layer positioned on the first gate insulating layer; a first conductive layer positioned on the first work function layer; and a first capping layer positioned on the first conductive layer. The first capping layer includes germanium oxide. A top surface of the first capping layer and a top surface of the capping mask layer are substantially coplanar.
1 . A semiconductor device, comprising:
a substrate;
a capping mask layer positioned on the substrate, wherein a trench is formed at the capping mask layer and is extended into the substrate;
a first gate insulating layer positioned along the capping mask layer, inwardly positioned in the substrate, and comprising a U-shaped cross-sectional profile, wherein the first gate insulating layer is conformally formed in the trench;
a first work function layer positioned on the first gate insulating layer and below the capping mask layer;
a first conductive layer positioned on the first work function layer and below the capping mask layer; and
a first capping layer positioned on the first conductive layer;
wherein the first capping layer comprises germanium oxide;
wherein a top surface of the first capping layer and a top surface of the capping mask layer are substantially coplanar;
wherein the first gate insulating layer, the first work function layer, the first conductive layer, and the first capping layer configure as a gate structure.
2 . The semiconductor device of claim 1 , wherein the first conductive layer comprises germanium, wherein the top surface of the first conductive layer is in direct contact with a bottom surface of the first capping layer while a bottom surface of the first conductive layer is in direct contact with a top surface of the first work function layer.
3 . The semiconductor device of claim 2 , wherein the first work function layer comprises silicon and/or germanium with substantially no oxygen and nitrogen.
4 . The semiconductor device of claim 3 , wherein the first gate insulating layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, a high-k material, or a combination thereof.
5 . The semiconductor device of claim 4 , wherein the capping mask layer comprises silicon oxide, silicon oxycarbide, silicon oxycarbonitride, silicon oxynitride, silicon nitride oxide, or a combination thereof.
6 . The semiconductor device of claim 1 , wherein the first work function layer, the first conductive layer, and the first capping layer are disposed in the trench and are in direct contact with the first gate insulating layer.
7 . The semiconductor device of claim 6 , wherein a top surface of the first gate insulating layer and the top surface of the capping mask layer are substantially coplanar.
8 . The semiconductor device of claim 6 , wherein a thickness of the first work function layer and a thickness of the first conductive layer are different, wherein a width of the first conductive layer and a width of the first capping layer are the same.
9 . The semiconductor device of claim 6 , wherein a thickness of the first work function layer and a thickness of the first conductive layer are substantially the same, wherein a width of the first conductive layer and a width of the first capping layer are the same.
10 . The semiconductor device of claim 6 , further comprising a second conductive layer positioned between the first conductive layer and the first capping layer, wherein the second conductive layer comprises molybdenum.
11 . The semiconductor device of claim 10 , further comprising a first liner layer positioned between the second conductive layer and the first conductive layer and between the second conductive layer and the first gate insulating layer, wherein the first liner layer comprises graphene or graphite.