Semiconductor device and method of forming the same
A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate trench crossing an active region, and a gate structure in the gate trench. The gate structure includes a gate dielectric layer disposed on an inner wall of the gate trench, a gate electrode disposed on the gate electric layer and partially filling the gate trench, a gate capping insulating layer disposed on the gate electrode, and a gap-fill insulating layer disposed in the gate trench and disposed on the gate capping insulating layer. The gate capping insulating layer includes a material formed by oxidizing a portion of the gate electrode, nitriding the portion of the gate electrode, or oxidizing and nitriding the portion of the gate electrode.
1. A semiconductor device comprising:
a gate trench crossing an active region; and
a gate structure in the gate trench,
wherein the gate structure includes:
a gate dielectric layer disposed on an inner wall of the gate trench;
a gate electrode disposed on the gate dielectric layer and partially filling the gate trench;
a gate capping insulating layer disposed on the gate electrode; and
a gap-fill insulating layer disposed in the gate trench and disposed on the gate capping insulating layer, and
wherein the gate capping insulating layer includes a silicon oxide layer formed by oxidizing a portion of the gate electrode, a silicon nitride layer formed by nitriding the portion of the gate electrode, or a silicon oxynitride layer formed by oxidizing and nitriding the portion of the gate electrode,
wherein the portion of the gate electrode adjacent to the gate capping insulating layer includes silicon,
wherein the gate capping insulating layer is not interposed between the gate dielectric layer and the gap-fill insulating layer, and
wherein a first thickness of the gate capping insulating layer is less than a second thickness of the gap-fill insulating layer.
2. The semiconductor device of claim 1 , wherein the gap-fill insulating layer includes a silicon nitride.
3. The semiconductor device of claim 1 , wherein the gate dielectric layer is interposed between the gate electrode and the inner wall of the gate trench, between the gate capping insulating layer and the inner wall of the gate trench, and between the gap-fill insulating layer and the inner wall of the gate trench.
4. The semiconductor device of claim 3 , further comprising an insulating layer formed on an inner wall of the gate dielectric layer and contacting a side wall of the gate capping insulating layer and a side wall of the gap-fill insulating layer.
5. The semiconductor device of claim 3 , further comprising a first impurity region and a second impurity region, wherein the first impurity region and the second impurity region are disposed in the active region and separated from each other by the gate trench.
6. The semiconductor device of claim 5 , further comprising a field region defining the active region, wherein the gate structure crosses the active region and extends into the field region.
7. The semiconductor device of claim 1 , wherein the gate electrode includes a lower gate electrode and an upper gate electrode on the lower gate electrode, the upper gate electrode being formed of silicon.
8. The semiconductor device of claim 7 , wherein the lower gate electrode includes a first lower gate electrode and a second lower gate electrode, the first lower gate electrode covering a bottom surface and a side surface of the second lower gate electrode.
9. A semiconductor device comprising:
a gate trench crossing an active region;
a gate structure in the gate trench,
wherein the gate structure includes:
a gate electrode;
a gap-fill insulating layer on the gate electrode;
a gate capping insulating layer between the gate electrode and the gap-fill insulating layer; and
a gate dielectric layer interposed between the gate electrode and an inner wall of the gate trench, between a side surface of the gate capping insulating layer and a side wall of the gate trench, and between a side surface of the gap-fill insulating layer and a side wall of the gate trench, the gap-fill insulating layer contacting a sidewall of the gate dielectric layer, and
wherein a first thickness of the gate capping insulating layer is less than a second thickness of the gap-fill insulating layer, and the gate capping insulating layer and the gate electrode include a common element,
wherein a portion of the gate electrode adjacent to the gate capping insulating layer includes a silicon material, and the gate capping insulating layer includes a silicon oxide, a silicon nitride, or a silicon oxynitride.
10. The semiconductor device of claim 9 , wherein the common element is silicon.
11. A semiconductor device comprising:
a gate trench crossing an active region;
a gate structure in the gate trench,
wherein the gate structure includes:
a gate electrode;
a gap-fill insulating layer on the gate electrode;
a gate capping insulating layer between the gate electrode and the gap-fill insulating layer; and
a gate dielectric layer interposed between the gate electrode and an inner wall of the gate trench, between a side surface of the gate capping insulating layer and a side wall of the gate trench, and between a side surface of the gap-fill insulating layer and a side wall of the gate trench, and
wherein a first thickness of the gate capping insulating layer is less than a second thickness of the gap-fill insulating layer, and the gate capping insulating layer and the gate electrode include a common element,
wherein the gate electrode includes a lower gate electrode and an upper gate electrode on the lower gate electrode,
the lower gate electrode includes a first material having a first resistivity lower than a second resistivity of a second material of the upper gate electrode, and
the lower gate electrode has a third thickness less than a fourth thickness of the upper gate electrode.
12. The semiconductor device of claim 11 , wherein the upper gate electrode is in contact with the gate capping insulating layer.