IP Library Granted Patent US 12,501,697
Granted Patent B2
US 12,501,697 · App. 18/657,175 · Granted Dec 16, 2025

Methods of forming semiconductor devices

Inventors: Wan-Yi Kao (Baoshan Township, TW); Szu-Ping Lee (Changhua County, TW); Che-Hao Chang (Hsinchu, TW); Chun-Heng Chen (Hsinchu, TW); Yung-Cheng Lu (Hsinchu, TW); Chi On Chui (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H10D84/853H10D30/024H10D30/6211H10D62/115H10D84/013H10D84/0158H10D84/038
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,501,697
App. No.
18/657,175
Granted
Dec 16, 2025
Kind
B2
Abstract

In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.

Claims (49)

1 . A method comprising:

forming a first fin and a second fin extending from a semiconductor substrate;

depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride;

depositing a fill material on the liner layer, the fill material formed of silicon;

annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing a thickness of the liner layer; and

recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.

2 . The method of claim 1 , wherein the thickness of the liner layer after the annealing is from 10% to 30% of the thickness of the liner layer before the annealing.

3 . The method of claim 1 , wherein the depositing the liner layer comprises:

placing the semiconductor substrate in a deposition chamber;

performing an atomic layer deposition cycle comprising:

introducing a silicon source precursor into the deposition chamber;

purging the silicon source precursor from the deposition chamber;

introducing an oxygen source precursor into the deposition chamber;

purging the oxygen source precursor from the deposition chamber;

introducing a nitrogen source precursor into the deposition chamber; and

purging the nitrogen source precursor from the deposition chamber; and

repeating the atomic layer deposition cycle.

4 . The method of claim 3 , wherein the oxygen source precursor reacts with the nitrogen source precursor to form OH bonds, and the silicon source precursor breaks the OH bonds.

5 . The method of claim 3 , wherein the atomic layer deposition cycle is repeated until the thickness of the liner layer is in a range of 15 Å to 50 Å.

6 . The method of claim 1 , wherein the annealing the liner layer and the fill material comprises:

annealing the liner layer and the fill material with a wet anneal process using steam.

7 . The method of claim 6 , wherein the wet anneal process is performed until the thickness of the liner layer is in a range of 1 Å to 10 Å.

8 . The method of claim 1 , wherein the recessing the liner layer and the fill material comprises:

etching the liner layer and the fill material with an etching process, wherein the annealing decreases an etching selectivity between the liner layer and the fill material relative to the etching process.

9 . A method comprising:

forming a first fin and a second fin extending from a semiconductor substrate;

depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration;

forming a fill material on the liner layer with a deposition process, the deposition process comprising:

depositing a semiconductor material on the liner layer; and

annealing the semiconductor material and the liner layer, the annealing converting the semiconductor material to the fill material, the annealing decreasing the nitrogen concentration of the liner layer; and

recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.

10 . The method of claim 9 , wherein the nitrogen concentration of the liner layer after the annealing is 10% of the nitrogen concentration of the liner layer before the annealing.

11 . The method of claim 9 , wherein the semiconductor material is silicon and the fill material is silicon oxide.

12 . The method of claim 9 , wherein the annealing decreases a thickness of the liner layer without eliminating the liner layer.

13 . The method of claim 9 , wherein the annealing does not oxidize the first fin or the second fin.

14 . The method of claim 9 , wherein the first fin and the second fin extend away from the semiconductor substrate in a first direction, and after the annealing, the nitrogen concentration of the liner layer decreases in the first direction.

15 . A method comprising:

forming a first fin and a second fin extending from a semiconductor substrate;

depositing a liner material along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate with a first deposition process;

forming a fill material on the liner material with a second deposition process, the second deposition process comprising:

depositing a semiconductor material on the liner material; and

annealing the semiconductor material and the liner material, the annealing converting the semiconductor material to the fill material, the annealing decreasing an etching selectivity between the liner material and the fill material relative to an etching process; and

recessing the liner material and the fill material by etching the liner material and the fill material with the etching process.

16 . The method of claim 15 , wherein the annealing decreases a thickness of the liner material.

17 . The method of claim 15 , wherein the annealing decreases a nitrogen concentration of the liner material.

18 . The method of claim 15 , wherein no oxidation of the first fin or the second fin occurs during the annealing.

19 . The method of claim 15 , wherein recessing the liner material and the fill material forms an isolation region between the first fin and the second fin, the method further comprising:

forming a gate structure on a top surface of the isolation region, the gate structure extending between the first fin and the second fin.

20 . The method of claim 15 , wherein the first deposition process is a different type of process than the second deposition process.

Continuity (3)
Continuation 17961949 · Oct 7, 2022
Continuation 17149950 · Jan 15, 2021
Related Publication 20240304628A1 · Sep 12, 2024
References Cited (22)
US 6498383B2 · Beyer et al. · 2002 [cited by applicant]
US 8796666B1 · Huang et al. · 2014 [cited by applicant]
US 10038093B2 · Sung et al. · 2018 [cited by applicant]
US 10971391B2 · Peng · 2021 [cited by applicant]
US 11069812B2 · Kao et al. · 2021 [cited by applicant]
US 11183423B2 · Chou · 2021 [cited by applicant]
US 11469229B2 · Kao · 2022 [cited by examiner]
US 20150028426A1 · Ching et al. · 2015 [cited by applicant]
US 20160322358A1 · Ching et al. · 2016 [cited by applicant]
US 20190067027A1 · Wang et al. · 2019 [cited by applicant]
US 20190067283A1 · Wang et al. · 2019 [cited by applicant]
US 20190157156A1 · Chen et al. · 2019 [cited by applicant]
US 20190165116A1 · Lim et al. · 2019 [cited by applicant]
US 20200161171A1 · Colombeau et al. · 2020 [cited by applicant]
CN 1528015A · 2004 [cited by applicant]
KR 20170027128A · 2017 [cited by applicant]
KR 20170043683A · 2017 [cited by applicant]
KR 20190024567A · 2019 [cited by applicant]
KR 20190062205A · 2019 [cited by applicant]
KR 20200037088A · 2020 [cited by applicant]
KR 20200058298A · 2020 [cited by applicant]
TW 202002077A · 2020 [cited by applicant]