Pixel and display device

1 . A pixel comprising:

a first capacitor electrically connected between a first node and a second node;

a second capacitor electrically connected between a first driving voltage line providing a first driving voltage and the first node;

a light emitting diode including a first electrode and a second electrode, the second electrode electrically connected with a second driving voltage line providing a second driving voltage;

a first transistor including a first electrode electrically connected with the first driving voltage line, a second electrode electrically connected with the first electrode of the light emitting diode, and a gate electrically connected with the second node;

a second transistor including a first electrode electrically connected with a data line, a second electrode electrically connected with the first node, and a gate receiving a scan signal;

a third transistor including a first electrode electrically connected with the first node, a second electrode electrically connected with a reference voltage line, and a gate receiving a compensation scan signal;

a fourth transistor including a first electrode directly electrically connected with the first electrode of the first transistor, a second electrode directly electrically connected with the first node, and a gate receiving an initialization scan signal;

a fifth transistor including a first electrode electrically connected with the second electrode of the first transistor, a second electrode electrically connected with the second node, and a gate receiving the compensation scan signal; and

a sixth transistor including a first electrode electrically connected with the second node, a second electrode electrically connected with a first initialization voltage line, and a gate receiving the initialization scan signal.

2 . The pixel of claim 1 , further comprising:

a seventh transistor including a first electrode electrically connected with the first driving voltage line, a second electrode electrically connected with the first electrode of the first transistor, and a gate receiving a first emission signal; and

an eighth transistor including a first electrode electrically connected with the first electrode of the light emitting diode, a second electrode electrically connected with the second electrode of the first transistor, and a gate receiving a second emission signal.

3 . The pixel of claim 2 , further comprising:

a ninth transistor including a first electrode electrically connected with the first electrode of the first transistor, a second electrode electrically connected with a bias voltage line providing a bias voltage, and a gate receiving an initialization signal; and

a tenth transistor including a first electrode electrically connected with a second initialization voltage line, a second electrode electrically connected with the first electrode of the light emitting diode, and a gate receiving the initialization signal.

4 . The pixel of claim 1 , wherein, during a first period, the initialization scan signal is at an active level.

5 . The pixel of claim 4 , wherein, during a second period continuous to the first period,

the scan signal, the initialization scan signal, and the compensation scan signal are at the active level, and

a test voltage is applied to the data line.

6 . The pixel of claim 5 , wherein, during the second period,

a level of the test voltage is identical to a level of a reference voltage provided to the reference voltage line, and

the data line and the first initialization voltage line are electrically connected.

7 . The pixel of claim 5 , wherein a saturation current is provided to the data line in the second period.

8 . The pixel of claim 5 , wherein, during a third period continuous to the second period, the compensation scan signal is at the active level.

9 . A display device comprising:

a display layer including a plurality of pixels, and operating in a test mode or a driving mode different from the test mode,

wherein each of the plurality of pixels includes:

a first capacitor electrically connected between a first node and a second node;

a second capacitor electrically connected between a first driving voltage line providing a first driving voltage and the first node;

a light emitting diode including a first electrode and a second electrode, the second electrode electrically connected with a second driving voltage line providing a second driving voltage;

a first transistor including a first electrode electrically connected with the first driving voltage line, a second electrode electrically connected with the first electrode of the light emitting diode, and a gate electrically connected with the second node;

a second transistor including a first electrode electrically connected with a data line, a second electrode electrically connected with the first node, and a gate receiving a scan signal;

a third transistor including a first electrode electrically connected with the first node, a second electrode electrically connected with a reference voltage line, and a gate receiving a compensation scan signal; and

a fourth transistor including a first electrode directly electrically connected with the first electrode of the first transistor, a second electrode directly electrically connected with the first node, and a gate receiving an initialization scan signal;

a fifth transistor including a first electrode electrically connected with the second electrode of the first transistor, a second electrode electrically connected with the second node, and a gate receiving the compensation scan signal; and

a sixth transistor including a first electrode electrically connected with the second node, a second electrode electrically connected with a first initialization voltage line, and a gate receiving the initialization scan signal.

10 . The display device of claim 9 , wherein each of the plurality of pixels further includes:

a seventh transistor including a first electrode electrically connected with the first driving voltage line, a second electrode electrically connected with the first electrode of the first transistor, and a gate receiving a first emission signal;

an eighth transistor including a first electrode electrically connected with the first electrode of the light emitting diode, a second electrode electrically connected with the second electrode of the first transistor, and a gate receiving a second emission signal;

a ninth transistor including a first electrode electrically connected with the first electrode of the first transistor, a second electrode electrically connected with a bias voltage line providing a bias voltage, and a gate receiving an initialization signal; and

a tenth transistor including a first electrode electrically connected with a second initialization voltage line, a second electrode electrically connected with the first electrode of the light emitting diode, and a gate receiving the initialization signal.

11 . The display device of claim 10 , wherein

the test mode includes a first test period, a second test period, and a third test period, and

during the first test period, the initialization scan signal is at an active level.

12 . The display device of claim 11 , wherein, during the second test period,

the scan signal, the initialization scan signal, and the compensation scan signal are at the active level, and

a test voltage is applied to the data line.

13 . The display device of claim 12 , wherein, during the second test period,

a level of the test voltage is identical to a level of a reference voltage provided to the reference voltage line, and

the data line and the first initialization voltage line are electrically connected.

14 . The display device of claim 12 , wherein a saturation current is provided to the data line in the second test period.

15 . The display device of claim 12 , wherein, during the third test period, the compensation scan signal is at the active level.

16 . The display device of claim 11 , wherein

the driving mode includes a first driving period to a fifth driving period,

during the first driving period, the first emission signal and the initialization scan signal are at the active level,

during the second driving period, the first emission signal and the compensation scan signal are at the active level, and

during the second driving period, the first node is electrically isolated from the first driving voltage line.

17 . The display device of claim 16 , wherein, during the third driving period, the scan signal is at the active level.

18 . The display device of claim 16 , wherein, during the fourth driving period, the initialization signal is at the active level.

19 . The display device of claim 16 , wherein, during the fifth driving period, the first emission signal and the second emission signal are at the active level.

20 . An electronic device comprising:

a display device comprising:

a display layer including a plurality of pixels, and operating in a test mode or a driving mode different from the test mode,

wherein each of the plurality of pixels includes:

a first capacitor electrically connected between a first node and a second node;

a second capacitor electrically connected between a first driving voltage line providing a first driving voltage and the first node;

a light emitting diode including a first electrode and a second electrode, the second electrode electrically connected with a second driving voltage line providing a second driving voltage;

a first transistor including a first electrode electrically connected with the first driving voltage line, a second electrode electrically connected with the first electrode of the light emitting diode, and a gate electrically connected with the second node;

a second transistor including a first electrode electrically connected with a data line, a second electrode electrically connected with the first node, and a gate receiving a scan signal;

a third transistor including a first electrode electrically connected with the first node, a second electrode electrically connected with a reference voltage line, and a gate receiving a compensation scan signal;

a fourth transistor including a first electrode directly electrically connected with the first electrode of the first transistor, a second electrode directly electrically connected with the first node, and a gate receiving an initialization scan signal;

a fifth transistor including a first electrode electrically connected with the second electrode of the first transistor, a second electrode electrically connected with the second node, and a gate receiving the compensation scan signal; and

a sixth transistor including a first electrode electrically connected with the second node, a second electrode electrically connected with a first initialization voltage line, and a gate receiving the initialization scan signal.