Asynchronous read circuit using delay sensing in magnetoresistive random access memory (MRAM)
View Patent ↗Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a data storage element; and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the data storage element. A delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The delay-sensing element is configured to sense a timing delay between a first signal on the active current path and a second signal on the reference current path. The delay-sensing element is further configured to determine a data state stored in the data storage element based on the timing delay.
1 . A memory device, comprising:
an active data path including a memory element;
reference data path including a reference memory element, the reference memory element having a resistance that differs from a resistance of the memory element; and
a delay-sensing element having a first input coupled to the active data path and a second input coupled to the reference data path;
wherein the delay-sensing element comprises:
a first NAND gate having a first first NAND gate input coupled to the active data path, a second first NAND gate input coupled to a second NAND gate output, and a first NAND gate output;
a second NAND gate having a first second NAND gate input coupled to the first NAND gate output, a second second NAND gate input coupled to the reference data path, and the second NAND gate output;
a third NAND gate having a first third NAND gate input coupled to the first NAND gate output, a second third NAND gate input coupled to a fourth NAND gate output, and a third NAND gate output; and
a fourth NAND gate having a first fourth NAND gate input coupled to the third NAND gate output, a second fourth NAND gate input coupled to the second NAND gate output, and the fourth NAND gate output.
2 . The memory device of claim 1 , wherein the delay-sensing element is configured to sense a timing delay between a first signal on the active data path and a second signal on the reference data path, the delay-sensing element further configured to determine a data state stored in the memory element based on the timing delay.
3 . The memory device of claim 1 , wherein the delay-sensing element is asynchronous.
4 . The memory device of claim 1 , wherein the memory element comprises a magnetic tunnel junction.
5 . The memory device of claim 1 ,
wherein the delay-sensing element is configured to determine a data state in the memory element is a first data state if a predetermined voltage on the active data path arrives before the predetermined voltage arrives on the reference data path.
6 . The memory device of claim 5 ,
wherein the delay-sensing element is further configured to determine the data state is a second data state if the predetermined voltage on the active data path arrives after the predetermined voltage arrives on the reference data path, the second data state being opposite the first data state.
7 . A memory device, comprising:
an active path including a data storage element;
a reference path; and
a first logic gate having a first first logic gate input coupled to the active path, a second first logic gate input coupled to a second logic gate output, and a first logic gate output;
a second logic gate having a first second logic gate input coupled to the first logic gate output, a second second logic gate input coupled to the reference path, and the second logic gate output;
a third logic gate having a first third logic gate input coupled to the first logic gate output, a second third logic gate input coupled to a fourth logic gate output, and a third logic gate output; and
a fourth logic gate having a first fourth logic gate input coupled to the third logic gate output, a second fourth logic gate input coupled to the second logic gate output.
8 . The memory device of claim 7 , wherein the first, second, third, and fourth logic gates are included in a delay-sensing element having a first input coupled to the active path and a second input coupled to the reference path.
9 . The memory device of claim 8 , wherein the delay-sensing element is configured to sense a timing delay between a first signal on the active path and a second signal on the reference path, the delay-sensing element further configured to determine a data state stored in the data storage element based on the timing delay.
10 . The memory device of claim 8 , wherein the delay-sensing element is asynchronous.
11 . The memory device of claim 8 , wherein the delay-sensing element is configured to determine when a predetermined voltage on the active path arrives before the predetermined voltage arrives on the reference path.
12 . The memory device of claim 11 ,
wherein the delay-sensing element is further configured to determine when the predetermined voltage on the active path arrives after the predetermined voltage arrives on the reference path.
13 . The memory device of claim 8 , wherein the reference path comprises a resistive element that has a resistance within an order of magnitude of a resistance of the data storage element.
14 . A memory device, comprising:
a data path including a memory cell;
a reference path including a reference element; and
means for sensing a timing delay between a first signal on the data path and a second signal on the reference path and for determining a data state stored in the memory cell based on the timing delay.
15 . The memory device of claim 14 , wherein the means for sensing the timing delay comprises:
a first logic circuit having a first first logic circuit input coupled to the data path, a second first logic circuit input coupled to a second logic circuit output, and a first logic circuit output;
a second logic circuit having a first second logic circuit input coupled to the first logic circuit output, a second second logic gate input coupled to the reference path, and the second logic circuit output;
a third logic circuit having a first third logic circuit input coupled to the first logic circuit output, a second third logic circuit input coupled to a fourth logic circuit output, and a third logic circuit output; and
a fourth logic circuit having a first fourth logic circuit input coupled to the third logic circuit output, a second fourth logic circuit input coupled to the second logic circuit output.
16 . The memory device of claim 14 , wherein the reference element has a fixed resistance that is an average of a first resistance corresponding to a first data state of the memory cell and a second resistance corresponding to a second data state of the memory cell.
17 . The memory device of claim 14 , wherein the memory cell has a ferromagnetic layer coupled to a source line, and a pinned layer coupled to a data storage node, and wherein the reference element on the reference path includes a reference data storage element.
18 . The memory device of claim 17 , further comprising:
a first access transistor disposed on the data path, the first access transistor having a first source/drain region coupled to the data storage node, a second source/drain region coupled to an data bitline, and a first gate coupled to a wordline;
a second access transistor disposed on the reference path, the second access transistor having a third source/drain region coupled to the reference element, a fourth source/drain region coupled to a reference bitline, and a second gate coupled to the wordline.
19 . The memory device of claim 14 , wherein the means for sensing the timing delay is an asynchronous circuit.
20 . The memory device of claim 14 , wherein the means for sensing the timing delay comprises:
a first stage having an input coupled to the data path; and
a second stage including a third input coupled to a first output of the first stage.