IP Library › Granted Patent US 12,511,053
Granted Patent B2
US 12,511,053 · App. 18/588,434 · Granted Dec 30, 2025

Memory system with hot page logic, an electronic system including the same memory system and a method of operating the same electronic system

Inventors: Dohyun Kim (Suwon-si, KR); Eui-young Chung (Suwon-si, KR); Seong Jun Yun (Suwon-si, KR); Jinwoo Choi (Suwon-si, KR); Yeri Heo (Suwon-si, KR)
Assignees: Samsung Electronics Co., Ltd.; UIF (University Industry Foundation), Yonsei University
G06F3/0614G06F3/0647G06F3/0673
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Quick Facts
Patent No.
US 12,511,053
App. No.
18/588,434
Granted
Dec 30, 2025
Kind
B2
Abstract

A memory system and an electronic system including the same are provided. The memory system includes a memory device configured to receive data, and a hot page logic configured to receive an address for the data, determine that the address is for a hot page based on an input frequency and an input order of the address, and create hot page information including the address that was determined as associated with the hot page such that a page migration operation of the data is performed.

Claims (56)

1 . A memory system, comprising:

a memory device configured to receive data; and

a hot page logic configured to receive an address for the data, configured to determine that the address is for a hot page based on an input frequency and an input order of the address, and configured to create hot page information including the address that was determined as associated with the hot page such that a page migration operation of the data is performed,

wherein the hot page logic is configured to collect frequency data based on the input frequency of the address that was received during a first time period that is predetermined, and configured to collect recency data based on the input order of a page frame indicated by the address, and

wherein the hot page logic is configured to perform a calculation operation on the frequency data and the recency data, compare a result of the calculation operation with a threshold value, and determine the page frame indicated by the address as the hot page.

2 . The memory system of claim 1 ,

wherein the hot page logic compares the result of the calculation operation with the threshold value based on an equation,

TH<Wf·FC+Wr·R

wherein TH is the threshold value, Wf is a frequency weight value coefficient, FC is a value of the frequency data, Wr is a recency weight value coefficient, and R is a value of the recency data.

3 . The memory system of claim 1 ,

wherein the hot page logic includes a special function register (SFR) that is configured to store a frequency weight value coefficient and a recency weight value coefficient used in the calculation operation, and the threshold value.

4 . The memory system of claim 3 ,

wherein the SFR is configured to change and provide at least one of the frequency weight value coefficient, the recency weight value coefficient, or the threshold value after creating the hot page information.

5 . The memory system of claim 3 ,

wherein data bandwidth of the memory device changes responsive to at least one of the frequency weight value coefficient, the recency weight value coefficient, or the threshold value stored in the SFR changing.

6 . The memory system of claim 1 ,

wherein after the first time period, the hot page logic is configured to perform a reset operation on the frequency data and the recency data that were collected.

7 . The memory system of claim 1 ,

wherein the address includes a first address and a second address,

wherein the frequency data includes a first frequency data for the first address and a second frequency data for the second address,

wherein the recency data includes a first recency data for the first address and a second recency data for the second address, and

wherein when the first address is input during the first time period, the hot page logic increases a value of the first frequency data.

8 . The memory system of claim 1 ,

wherein the address includes a first address and a second address,

wherein the frequency data includes a first frequency data for the first address and a second frequency data for the second address,

wherein the recency data includes a first recency data for the first address and a second recency data for the second address,

wherein a value of the first recency data is less than a value of the second recency data, and

wherein when a third address is input in addition to the first address and the second address during the first time period, the hot page logic resets the first frequency data and the first recency data.

9 . The memory system of claim 8 ,

wherein the hot page logic is configured to store a third frequency data and a third recency data corresponding to the third address, and

wherein a value of the third recency data that is stored is greater than a value of the first recency data.

10 . An electronic system, comprising:

a processor configured to output data and an address of the data;

a first memory system including a first memory device configured to receive the data and a hot page logic configured to receive the address and configured to output hot page information based on an input frequency and an input order of the address; and

a second memory system including a second memory device different from the first memory device,

wherein a page migration operation for the data is performed based on the hot page information, and

wherein the processor comprises a performance management unit configured to measure a first data bandwidth of the data that is input to the first memory device and configured to measure a second data bandwidth of the data that is input to the second memory device.

11 . The electronic system of claim 10 ,

wherein a latency time of the first memory system is longer than a latency time of the second memory system.

12 . The electronic system of claim 10 ,

wherein if a ratio of the first data bandwidth and the second data bandwidth is different from a predetermined bandwidth ratio, the page migration operation is performed in the second memory system.

13 . The electronic system of claim 10 , further comprising:

a CXL switch that is configured to enable the first memory system and the second memory system to communicate with each other,

wherein the first memory system is configured to provide the hot page information to the second memory system through the CXL switch.

14 . A method of operating an electronic system, comprising:

collecting frequency data and recency data of an address in a first memory system based on an input frequency and an input order of the address for a first data that is input to the first memory system;

measuring a first data bandwidth of the first data and a second data bandwidth of a second data that is input to a second memory system different from the first memory system;

performing a calculation operation on the frequency data and the recency data in response to a ratio of the first data bandwidth and the second data bandwidth;

creating hot page information indicating whether the address is a hot page based on the calculation operation; and

migrating a page for the first data based on the hot page information.

15 . The method of operating the electronic system of claim 14 ,

wherein if the ratio of the first data bandwidth and the second data bandwidth is different from a predetermined bandwidth ratio, performing the calculation operation on the frequency data and the recency data.

16 . The method of operating the electronic system of claim 15 , further comprising:

providing a frequency weight value coefficient and a recency weight value coefficient used in the calculation operation for the frequency data and the recency data, and a threshold value corresponding to a result of the calculation operation, based on the ratio of the first data bandwidth and the second data bandwidth.

17 . The method of operating the electronic system of claim 14 ,

wherein the creating of the hot page information comprises determining whether the address is associated with a hot page by comparing a result of the calculation operation with a threshold value.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2024
From: KIM, DOHYUN; CHUNG, EUI-YOUNG; YUN, SEONG JUN; CHOI, JINWOO; HEO, YERI
To: SAMSUNG ELECTRONICS CO., LTD.; UIF (UNIVERSITY INDUSTRY FOUNDATION), YONSEI UNIVERSITY
Reel/Frame 066575/0080 →
Priority Claims (1)
KR 10-2023-0102914 · Aug 7, 2023 · national
Continuity (1)
Related Publication 20250053304A1 · Feb 13, 2025
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