Storage of machine check exceptions
Examples described herein relate to circuitry to copy reported error data to a data structure in memory. In some examples, the reported error data includes a last reported error and at least one other reported error. In some examples, the circuitry utilizes a direct memory access (DMA) circuitry to copy the reported error data to the data structure in memory.
1 . An apparatus comprising:
an interface and
circuitry, coupled to the interface, the circuitry to copy a batch of multiple reported error data to a data structure in memory, wherein:
the circuitry comprises a direct memory access (DMA) circuitry to copy the multiple reported error data to the data structure in memory,
the batch of multiple reported error data includes a last reported error and at least one other reported error,
the multiple reported error data comprises error reporting of different components of a system on chip (SoC), and
the different components of the SoC comprise one or more of a power control unit (PCU), a memory controller (MC), or a cache and home agent (CHA).
2 . The apparatus of claim 1 , wherein the data structure comprises multiple linked lists and at least one linked list is associated with errors reported by a particular sub-system.
3 . The apparatus of claim 1 , wherein the data structure is accessible to a management controller.
4 . The apparatus of claim 3 , wherein the management controller is positioned on a different system on chip than that of the circuitry.
5 . The apparatus of claim 1 , comprising a system agent, wherein the system agent comprises the circuitry.
6 . The apparatus of claim 5 , wherein the system agent includes four or more of: a memory controller, a shared cache, a cache coherency manager, arithmetic logic units, floating point units, core or processor interconnects, Caching/Home Agent (CHA), or bus or link controllers.
7 . The apparatus of claim 1 , comprising a processor to execute a process to program a pointer to the data structure in memory wherein the pointer is utilized by logging circuitry to identify the data structure in memory.
8 . At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
configure circuitry to copy multiple reported error data to a data structure in memory, wherein:
the multiple reported error data includes a last reported error and at least one other reported error,
the circuitry comprises a direct memory access (DMA) circuitry to copy the multiple reported error data to the data structure in memory,
the multiple reported error data comprises error reporting of different portions of a system on chip (SoC), and
the different portions of the SoC comprise one or more of a power control unit (PCU), a memory controller (MC), or a cache and home agent (CHA).
9 . The computer-readable medium of claim 8 , wherein the data structure comprises multiple linked lists and at least one linked list is associated with errors reported by a particular sub-system.
10 . The computer-readable medium of claim 8 , wherein the data structure is accessible to a management controller.
11 . The computer-readable medium of claim 10 , wherein the management controller is positioned on a different system on chip than that of the circuitry.
12 . The computer-readable medium of claim 8 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
identify a pointer to the data structure in memory.
13 . A method comprising:
copying multiple reported error data to a data structure in memory, wherein;
the multiple reported error data includes a last reported error and at least one other reported error,
the copying comprises using a direct memory access (DMA) circuitry to copy the multiple reported error data to the data structure in memory
the multiple reported error data comprises error reporting of different portions of a system on chip (SoC), and
the different portions of the SoC comprise one or more of a power control unit (PCU), a memory controller (MC), or a cache and home agent (CHA).
14 . The method of claim 13 , wherein the data structure comprises multiple linked lists and at least one linked list is associated with errors reported by a particular sub-system.
15 . The method of claim 13 , wherein the data structure is accessible to a management controller.