Solid-state imaging device
View Patent ↗According to one embodiment, there is a solid-state imaging device including a chip. The chip includes a pixel array, a plurality of signal lines, a plurality of output circuits and a plurality of output terminals. In the pixel array, a plurality of pixel groups each including two or more pixels is arrayed at least in a column direction. The plurality of signal lines corresponds to the plurality of pixel groups, each of the plurality of signal lines being connected to a corresponding pixel group. The plurality of output circuits corresponds to the plurality of signal lines, each of the plurality of output circuits being connected to a corresponding signal line. The plurality of output terminals corresponds to the plurality of output circuits, each of the plurality of output terminals being connected to a corresponding output circuit.
1 . A solid-state imaging device comprising a chip, wherein
the chip includes
a pixel array in which a plurality of pixel groups each including two or more pixels is arrayed at least in a column direction,
a plurality of signal lines that corresponds to the plurality of pixel groups, each of the plurality of signal lines being connected to a corresponding pixel group,
a plurality of output circuits that corresponds to the plurality of signal lines, each of the plurality of output circuits being connected to a corresponding signal line, and
a plurality of output terminals that corresponds to the plurality of output circuits, each of the plurality of output terminals being connected to a corresponding output circuit.
2 . The solid-state imaging device according to claim 1 , wherein
the chip further includes a control circuit that is connected to each of the plurality of output circuits.
3 . The solid-state imaging device according to claim 2 , wherein
the control circuit controls the plurality of output circuits such that signals are serially output from the plurality of output circuits to the plurality of output terminals.
4 . The solid-state imaging device according to claim 2 , wherein
the control circuit controls the plurality of output circuits such that signals are output from the plurality of output circuits to the plurality of output terminals in parallel.
5 . The solid-state imaging device according to claim 2 , wherein
the plurality of output circuits is grouped into a plurality of output circuit groups each including two or more output circuits,
the plurality of output terminals is grouped into a plurality of output terminal groups each including two or more output terminals, and
the control circuit controls the plurality of output circuits such that signals are output from the plurality of output circuit groups to the plurality of output terminal groups in parallel, and signals are serially output from two or more output circuits in each of the plurality of output circuit groups to two or more output terminals in the output terminal groups.
6 . The solid-state imaging device according to claim 2 , wherein
the control circuit controls presence or absence of signal output to the plurality of output terminals for each of the plurality of output circuits.
7 . The solid-state imaging device according to claim 1 , wherein
the chip further includes a scanning circuit that scans the pixel array in a column direction, and
the scanning circuit includes a plurality of circuit blocks corresponding to the plurality of pixel groups.
8 . The solid-state imaging device according to claim 1 , further comprising:
an analog front end; and
a signal wire that connects the plurality of output terminals and the analog front end in parallel.
9 . The solid-state imaging device according to claim 1 , further comprising:
an analog front end; and
a signal wire that connects the plurality of output terminals and the analog front end serially.
10 . The solid-state imaging device according to claim 1 , wherein
the plurality of output terminals is grouped into a plurality of output terminal groups each including two or more output terminals, and
the solid-state imaging device further comprises:
an analog front end; and
a signal wire that connects the plurality of output terminal groups and the analog front end in parallel and connects the two or more output terminals and the analog front end serially.
11 . The solid-state imaging device according to claim 1 , further comprising:
an analog front end that is separated from the chip in a longitudinal direction of the chip; and
a signal wire that connects the plurality of output terminals and the analog front end.
12 . The solid-state imaging device according to claim 11 , wherein
the analog front end includes a first input terminal, a second input terminal, and a third input terminal,
the plurality of output terminals includes a first output terminal, a second output terminal, and a third output terminal, and
the signal wire includes
a first line that connects the first output terminal and the first input terminal while forming an L shape,
a second line that connects the second output terminal and the second input terminal while forming an L shape larger than the first line, and
a third line that connects the third output terminal and the third input terminal while forming an L shape larger than the second line.
13 . The solid-state imaging device according to claim 11 , wherein
the analog front end includes a first input terminal,
the plurality of output terminals includes a first output terminal, a second output terminal, and a third output terminal, and
the signal wire includes
a first line that connects the first output terminal and the first input terminal while forming an L shape,
a second line that connects the second output terminal and the first line, and
a third line that connects the third output terminal and the first line.
14 . The solid-state imaging device according to claim 11 , wherein
the analog front end includes a first input terminal and a second output terminal,
the plurality of output terminals includes a first output terminal, a second output terminal, and a third output terminal, and
the signal wire includes
a first line that connects the first output terminal and the first input terminal while forming an L shape,
a second line that connects the second output terminal and the first line, and
a third line that connects the third output terminal and the second output terminal while forming an L shape larger than the first line.
15 . The solid-state imaging device according to claim 1 , comprising
a plurality of the chips,
the solid-state imaging device further comprising
an analog front end to which the plurality of chips is connected.
16 . The solid-state imaging device according to claim 15 , further comprising
a signal wire that connects the plurality of chips and the analog front end serially.
17 . The solid-state imaging device according to claim 16 , wherein
the signal wire connects the plurality of output terminals of each of the plurality of chips and the analog front end serially.
18 . The solid-state imaging device according to claim 16 , wherein
the signal wire connects the plurality of output terminals of each of the plurality of chips and the analog front end in parallel.
19 . The solid-state imaging device according to claim 16 , wherein
in each of the plurality of chips, the plurality of output terminals is grouped into a plurality of output terminal groups each including two or more output terminals, and
the signal wire connects the plurality of output terminal groups of each of the plurality of chips and the analog front end in parallel and connects the two or more output terminals and the analog front end serially.
20 . The solid-state imaging device according to claim 15 , wherein
the plurality of chips is arranged in a longitudinal direction of the chip, and
the analog front end is separated from the plurality of chips in the longitudinal direction.