Solid-state imaging element, imaging device, and control method of solid-state imaging element
An object is to reduce a circuit scale in a solid-state imaging element that detects an address event. The solid-state imaging element is provided with a plurality of photoelectric conversion elements, a signal supply unit, and a detection unit. In this solid-state imaging element, each of the plurality of photoelectric conversion elements photoelectrically converts incident light to generate a first electric signal. Furthermore, in the solid-state imaging element, the detection unit detects whether or not a change amount of the first electric signal of each of the plurality of photoelectric conversion elements exceeds a predetermined threshold and outputs a detection signal indicating a result of the detection result.
1. A solid-state imaging device comprising:
a plurality of detection pixels that each output a luminance change of incident light;
a detection circuit that outputs an event signal based on the luminance change output from each of the detection pixels; and
a first common line connecting the plurality of detection pixels to each other,
wherein each of the detection pixels includes:
a photoelectric conversion element;
a logarithmic conversion circuit that converts a photocurrent flowing out of the photoelectric conversion element into a voltage signal corresponding to a logarithmic value of the photocurrent;
a first circuit that outputs a luminance change of incident light incident on the photoelectric conversion element based on the voltage signal output from the logarithmic conversion circuit;
a first transistor connected between the photoelectric conversion element and the logarithmic conversion circuit; and
a second transistor connected between the photoelectric conversion element and the first common line, wherein
the detection circuit includes a second circuit that outputs the event signal based on the luminance change output from each of the detection pixels.
2. The solid-state imaging device according to claim 1 , wherein the second transistor is connected between the first common line and a node, the node being configured to connect the photoelectric conversion element and the first transistor.
3. The solid-state imaging device according to claim 1 , further comprising:
a readout circuit that is connected to the first common line and that generates a pixel signal having a voltage value corresponding to charge accumulated in the photoelectric conversion element.
4. The solid-state imaging device according to claim 3 , wherein the readout circuit includes:
a reset transistor connected between the first common line and a power supply line; and
an amplification transistor having a gate connected to the first common line.
5. The solid-state imaging device according to claim 1 , wherein each of the detection pixels further includes a differentiator that generates a differential signal indicating a conversion amount of the voltage signal output from the logarithmic conversion circuit.
6. The solid-state imaging device according to claim 1 , wherein
the detection circuit is one of a plurality of detection circuits,
each of the detection circuits is configured to output a request for requesting readout of a detection signal from the detection circuit when having detected an address event in at least one of the plurality of detection pixels, and
an arbiter configured to arbitrate the request output from at least one of the plurality of detection circuits and determine a readout order of the detection signal for the detection circuit that has output the request.
7. The solid-state imaging device according to claim 1 , further comprising:
a first chip including a light receiving section, the light receiving section having a plurality of logarithmic response sections being arranged in a two-dimensional lattice pattern, each of the plurality of logarithmic response sections including the photoelectric conversion element, the logarithmic conversion circuit, the first transistor, and the second transistor.
8. The solid-state imaging device according to claim 7 , wherein the logarithmic conversion circuit includes:
a third transistor having a source connected to the first transistor; and
a fourth transistor having a gate connected to the source of the third transistor and having a source grounded, the third transistor having a gate connected to a drain of the fourth transistor.
9. The solid-state imaging device according to claim 7 ,
wherein the light receiving section further includes a pixel isolation section extending in a lattice pattern, and
each of the logarithmic response sections is provided in each of pixel regions partitioned into the two-dimensional lattice pattern by the pixel isolation section.
10. The solid-state imaging device according to claim 9 ,
wherein the first and second transistors, at least two transistors different from the first and second transistors, and the photoelectric conversion element are disposed in the pixel region,
the at least two transistors are disposed at positions across the photoelectric conversion element in the pixel region, and
the logarithmic conversion circuit is constituted by using at least one of the at least two transistors in each of the two pixel regions adjacent to each other.
11. The solid-state imaging device according to claim 7 , wherein the detection circuit is one of a plurality of detection circuits, and further comprising a second chip on which a plurality of the detection circuits is disposed, wherein the first chip and the second chip constitute a single stacked chip.
12. An imaging device comprising:
the solid-state imaging device according to claim 1 ; and
a control section that controls the solid-state imaging device.
13. The imaging device according to claim 12 , wherein the second transistor is connected between the first common line and a node, the node being configured to connect the photoelectric conversion element and the first transistor.
14. The imaging device according to claim 12 , further comprising:
a readout circuit that is connected to the first common line and that generates a pixel signal having a voltage value corresponding to charge accumulated in the photoelectric conversion element.
15. The imaging device according to claim 14 , wherein the readout circuit includes:
a reset transistor connected between the first common line and a power supply line; and
an amplification transistor having a gate connected to the first common line.
16. The imaging device according to claim 12 , wherein each of the detection pixels further includes a differentiator that generates a differential signal indicating a conversion amount of the voltage signal output from the logarithmic conversion circuit.
17. The imaging device according to claim 12 , wherein
the detection circuit is one of a plurality of detection circuits,
each of the detection circuits is configured to output a request for requesting readout of a detection signal from the detection circuit when having detected an address event in at least one of the plurality of detection pixels, and
an arbiter configured to arbitrate the request output from at least one of the plurality of detection circuits and determine a readout order of the detection signal for the detection circuit that has output the request.
18. The imaging device according to claim 12 , further comprising:
a first chip including a light receiving section, the light receiving section having a plurality of logarithmic response sections being arranged in a two-dimensional lattice pattern, each of the plurality of logarithmic response sections including the photoelectric conversion element, the logarithmic conversion circuit, the first transistor, and the second transistor.
19. The imaging device according to claim 18 , wherein the logarithmic conversion circuit includes:
a third transistor having a source connected to the first transistor; and
a fourth transistor having a gate connected to the source of the third transistor and having a source grounded, the third transistor having a gate connected to a drain of the fourth transistor.
20. The imaging device according to claim 18 ,
wherein the light receiving section further includes a pixel isolation section extending in a lattice pattern, and
each of the logarithmic response sections is provided in each of pixel regions partitioned into the two-dimensional lattice pattern by the pixel isolation section.