Instructions and support for calculating prefix sums
Techniques for performing prefix sums in response to a single instruction are describe are described. In some examples, the single instruction includes fields for an opcode, one or fields to reference a first source operand, one or fields to reference a second source operand, one or fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least: perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand.
1 . An apparatus comprising:
decoder circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode, one or fields to reference a first source operand, one or fields to reference a second source operand, one or fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least:
perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and
store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand; and
execution circuitry configured to execute the decoded instruction according to the opcode.
2 . The apparatus of claim 1 , wherein the one or more fields to reference the first source operand identify a vector register.
3 . The apparatus of claim 1 , wherein the one or more fields to reference the first source operand identify a vector register identify a memory location.
4 . The apparatus of claim 1 , wherein packed data elements of the first and second sources are of a datatype unsigned integer, signed integer, and floating point.
5 . The apparatus of claim 4 , wherein packed data elements of the first and second sources are 8-bit, 16-bit, 32-bit, or 64-bit in size.
6 . The apparatus of claim 1 , wherein the instance of the single instruction further comprises a field for a prefix, wherein the prefix provides one or more fields to reference a mask operand and one or more bits to be used to reference the at least one of the sources.
7 . The apparatus of claim 6 , wherein the execution circuitry is to use the mask operand to determine which data element positions of the destination operand to write.
8 . The apparatus of claim 6 , the execution circuitry is to use the mask operand to determine which data element positions of the second source to unmask.
9 . A method comprising:
decoding an instance of a single instruction, the single instruction including fields for an opcode, one or more fields to reference a first source operand, one or more fields to reference a second source operand, one or more fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least:
perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and
store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand; and
executing the decoded instruction according to the opcode.
10 . The method of claim 9 , wherein the one or more fields to reference the first source operand identify a vector register.
11 . The method of claim 9 , wherein the one or more fields to reference the first source operand identify a vector register identify a memory location.
12 . The method of claim 9 , wherein packed data elements of the first and second sources are of a datatype unsigned integer, signed integer, and floating point.
13 . The method of claim 12 , wherein packed data elements of the first and second sources are 8-bit, 16-bit, 32-bit, or 64-bit in size.
14 . The method of claim 9 , wherein the instance of the single instruction further comprises a field for a prefix, wherein the prefix provides one or more fields to reference a mask operand and one or more bits to be used to reference the at least one of the sources.
15 . The method of claim 14 , wherein the executing is to use the mask operand to determine which data element positions of the destination operand to write.
16 . The method of claim 14 , the executing is to use the mask operand to determine which data element positions of the second source to unmask.
17 . A method comprising:
translating an instance of a single instruction of a first instruction set architecture to one or more instructions of a second instruction set architecture, the single instruction including fields for an opcode, one or more fields to reference a first source operand, one or more fields to reference a second source operand, one or more fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least:
perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and
store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand; and
decoding the one or more instructions of the second instruction set architecture;
executing the decoded one or more instructions of the second instruction set architecture instruction according to the opcode of the single instruction of the first instruction set architecture.
18 . The method of claim 17 , wherein the one or more fields to reference the first source operand identify a vector register.
19 . The method of claim 17 , wherein the one or more fields to reference the first source operand identify a vector register identify a memory location.
20 . The method of claim 17 , wherein packed data elements of the first and second sources are of a datatype unsigned integer, signed integer, and floating point.
21 . The method of claim 20 , wherein packed data elements of the first and second sources are 8-bit, 16-bit, 32-bit, or 64-bit in size.
22 . The method of claim 21 , wherein the instance of the single instruction further comprises a field for a prefix, wherein the prefix provides one or more fields to reference a mask operand and one or more bits to be used to reference the at least one of the sources.
23 . The method of claim 22 , wherein the executing is to use the mask operand to determine which data element positions of the destination operand to write.
24 . The method of claim 22 , the executing is to use the mask operand to determine which data element positions of the second source to unmask.
25 . A system comprising:
memory to store an instance of a single instruction; and
a processor core comprising:
decoder circuitry to decode an instance of the single instruction, the single instruction to include fields for an opcode, one or more fields to reference a first source operand, one or more fields to reference a second source operand, one or more fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least:
perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and
store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand; and
execution circuitry configured to execute the decoded instruction according to the opcode.