Rollback of processor microcode updates in runtime without system reboot
Techniques for updates and rollbacks of firmware patches in a computing system during runtime are provided. A processor includes one or more intellectual property (IP) blocks; a secure patch memory to store a first firmware patch in a primary patch region and a second firmware patch in a secondary patch region; a processing core to execute a first patch commit instruction; and a security controller to send the second firmware patch to the one or more IP blocks, set the secondary patch region to the primary patch region when the first patch commit instruction indicates the second firmware patch is valid, and get the first firmware patch from the primary patch region and send the first firmware patch to the one or more IP blocks when the first patch commit instruction indicates the second firmware patch is invalid.
1 . An apparatus comprising:
one or more intellectual property (IP) blocks;
a secure patch memory to store a first firmware patch in a primary patch region and a second firmware patch in a secondary patch region, wherein the secure patch memory comprises a plurality of primary patch regions and a plurality of secondary patch regions associated with the plurality of primary patch regions, each of the primary patch regions and the secondary patch regions storing firmware patches for a selected one or more of the one or more IP blocks;
a processing core to execute a first patch commit instruction; and
a security controller to send the second firmware patch to the one or more IP blocks, set the secondary patch region to the primary patch region when the first patch commit instruction indicates the second firmware patch is valid, and get the first firmware patch from the primary patch region and send the first firmware patch to the one or more IP blocks when the first patch commit instruction indicates the second firmware patch is invalid.
2 . The apparatus of claim 1 , wherein the secure patch memory comprises a primary save state region to store register values modified by the first firmware patch and a secondary save state region to store register values modified by the second firmware patch and the security controller is to store the register values modified by the second firmware patch into the secondary save state region.
3 . The apparatus of claim 2 , the security controller to get the register values from the primary save state region and send the register values from the primary save state region to the one or more IP blocks when the first patch commit instruction indicates the second firmware patch is invalid.
4 . The apparatus of claim 1 , the processing core to execute a second patch commit instruction, the second patch commit instruction indicating an address of the second firmware patch in a system memory, and the security controller to get the second firmware patch from the system memory at the address and store the second firmware patch in the secondary patch region in the secure patch memory.
5 . The apparatus of claim 4 , the processing core to receive the first patch commit instruction and the second patch commit instruction from one of an operating system and a baseboard management controller.
6 . The apparatus of claim 1 , wherein one of an operating system and a baseboard management controller determines if the second firmware patch is valid or invalid.
7 . The apparatus of claim 1 , wherein the processing core to execute a first patch commit instruction; and the security controller to send the second firmware patch to the one or more IP blocks, set the secondary patch region to the primary patch region when the first patch commit instruction indicates the second firmware patch is valid, and get the first firmware patch from the primary patch region and send the first firmware patch to the one or more IP blocks when the first patch commit instruction indicates the second firmware patch is invalid, during runtime of a computing system including the processing core and the security controller.
8 . The apparatus of claim 1 , wherein the secure patch memory and the security controller are on a same die as the processing core.
9 . The apparatus of claim 1 , wherein the secure patch memory is accessible only by the security controller.
10 . The apparatus of claim 1 , wherein the first firmware patch and the second firmware patch comprise a plurality of binary images, each of the plurality of binary images for a selected one or more IP blocks.
11 . A method comprising:
storing a first firmware patch in a primary patch region of a secure patch memory in a processor and a second firmware patch in a secondary patch region in the secure patch memory, wherein the secure patch memory comprises a plurality of primary patch regions and a plurality of secondary patch regions associated with the plurality of primary patch regions, each of the primary patch regions and the secondary patch regions storing firmware patches for a selected one or more of one or more intellectual property (IP) blocks of a processor;
executing, by a core of the processor, a first patch commit instruction; and
sending, by a security controller of the processor, the second firmware patch to the one or more IP blocks of the processor, setting the secondary patch region to the primary patch region when the first patch commit instruction indicates the second firmware patch is valid, and getting the first firmware patch from the primary patch region and sending the first firmware patch to the one or more IP blocks when the first patch commit instruction indicates the second firmware patch is invalid.
12 . The method of claim 11 , comprising storing register values modified by the first firmware patch in a primary save state region of the secure patch memory and storing register values modified by the second firmware patch and in a secondary save state region of the secure patch memory.
13 . The method of claim 12 , comprising getting, by the security controller, the register values from the primary save state region and sending the register values from the primary save state region to the one or more IP blocks when the first patch commit instruction indicates the second firmware patch is invalid.
14 . The method of claim 11 , comprising executing a second patch commit instruction, the second patch commit instruction indicating an address of the second firmware patch in a system memory, and getting, by the security controller, the second firmware patch from the system memory at the address and storing the second firmware patch in the secondary patch region in the secure patch memory.
15 . The method of claim 14 , comprising receiving, by the core, the first patch commit instruction and the second patch commit instruction from one of an operating system and a baseboard management controller.
16 . The method of claim 11 , comprising determining, by one of an operating system and a baseboard management controller, if the second firmware patch is valid or invalid.
17 . The method of claim 11 , comprising executing, by the core, a first patch commit instruction; and sending, by the security controller, the second firmware patch to the one or more IP blocks, setting the secondary patch region to the primary patch region when the first patch commit instruction indicates the second firmware patch is valid, and getting the first firmware patch from the primary patch region and sending the first firmware patch to the one or more IP blocks when the first patch commit instruction indicates the second firmware patch is invalid, during runtime of a computing system including the core and the security controller.
18 . A system, comprising:
a system memory to store a first firmware patch and a second firmware patch; and
a processor, the processor including:
one or more intellectual property (IP) blocks;
a secure patch memory to store a first firmware patch in a primary patch region and a second firmware patch in a secondary patch region, wherein the secure patch memory comprises a plurality of primary patch regions and a plurality of secondary patch regions associated with the plurality of primary patch regions, each of the primary patch regions and the secondary patch regions storing firmware patches for a selected one or more of the one or more IP blocks;
a processing core to execute a first patch commit instruction; and
a security controller to send the second firmware patch to the one or more IP blocks, set the secondary patch region to the primary patch region when the first patch commit instruction indicates the second firmware patch is valid, and get the first firmware patch from the primary patch region and send the first firmware patch to the one or more IP blocks when the first patch commit instruction indicates the second firmware patch is invalid.
19 . The system of claim 18 , wherein the secure patch memory comprises a primary save state region to store register values modified by the first firmware patch and a secondary save state region to store register values modified by the second firmware patch and the security controller is to store the register values modified by the second firmware patch into the secondary save state region.
20 . The system of claim 19 , the security controller to get the register values from the primary save state region and send the register values from the primary save state region to the one or more IP blocks when the first patch commit instruction indicates the second firmware patch is invalid.
21 . The system of claim 18 , the processing core to execute a second patch commit instruction, the second patch commit instruction indicating an address of the second firmware patch in a system memory, and the security controller to get the second firmware patch from the system memory at the address and store the second firmware patch in the secondary patch region in the secure patch memory.
22 . The system of claim 18 , wherein the processing core to execute a first patch commit instruction; and the security controller to send the second firmware patch to the one or more IP blocks, set the secondary patch region to the primary patch region when the first patch commit instruction indicates the second firmware patch is valid, and get the first firmware patch from the primary patch region and send the first firmware patch to the one or more IP blocks when the first patch commit instruction indicates the second firmware patch is invalid, during runtime of a computing system including the processing core and the security controller.
23 . The system of claim 18 , wherein the secure patch memory and the security controller are on a same die as the processing core.
24 . The system of claim 18 , wherein the secure patch memory is accessible only by the security controller.