Storage controller with improved write amplification characteristics and storage device including the same
A storage controller for writing first data to a first memory cell by performing programming of the first memory cell N-times, where N is a positive integer greater than 1, includes a write amplification manager and a central processing unit. The write amplification manager checks whether the first data is invalid data before an N th programming of the first memory cell is performed, and the central processing unit does not perform the N-th programming of the first memory cell when the first data is the invalid data.
1 . A storage device for writing first data to a first memory block and writing second data to a second memory block by performing programming of each of the first memory block and the second memory block N-times, N being a positive integer greater than 1, the storage device comprising:
a non-volatile memory (NVM) device comprising the first memory block and the second memory block; and
a storage controller configured to write the first data to cells of the first memory block and write the second data to cells of the second memory block,
wherein the storage controller comprises:
a write amplification (WAF) manager comprising an open memory cell detector configured to check whether an open memory cell exists in the first memory block or the second memory block before an Nth programming of the first memory block and the second memory block is performed, and a memory cell compactor configured to conduct memory cell compaction by moving a location of an (N−1)th-programming of a memory cell in one memory block of the first memory block and the second memory block to a memory cell in the other memory block of the first memory block and the second memory block when the open memory cell exists in the first memory block or the second memory block; and
a central processing unit (CPU) configured to not perform the Nth programming of the first memory block and the second memory block after the memory cell compactor conducts the memory cell compaction.
2 . The storage device of claim 1 , wherein the memory cell compaction is conducted by moving the location of the (N−1)th-programming of the memory cell in the one memory block to a memory block having fewer open memory cells.
3 . The storage device of claim 2 , wherein the memory cell whose (N−1)th-programming location is moved is a memory cell existing on a word line of a same order in the first memory block and the second memory block.
4 . The storage device of claim 1 , wherein the open memory cell is an empty memory cell of a last word line that is (N−1)th programmed in the first memory block or the second memory block.
5 . The storage device of claim 4 , wherein, when the open memory cell does not exist, the memory cell compaction is not conducted.
6 . The storage device of claim 1 , wherein the NVM device further comprises a third memory block and the storage controller writes third data to the third memory block by performing programming of the third memory block N-times, and
wherein the open memory cell detector is configured to detect the open memory cell existing in the first memory block and the second memory block before the storage controller performs an Nth programming of the third memory block.
7 . A method for writing first data to a first memory block of a storage device and writing second data to a second memory block of the storage device, the method comprising:
programming each of the first memory block and the second memory block (N−1)-times to write the first data to the first memory block and the second data to the second memory block, N being a positive integer greater than 1;
checking whether an open memory cell exists in the first memory block or the second memory block before an Nth programming of the first memory block and the second memory block is performed;
conducting memory cell compaction by moving a location of the (N−1)th-programming of a memory cell in one memory block of the first memory block and the second memory block to a memory cell in the other memory block of the first memory block and the second memory block when the open memory cell exists in the first memory block or the second memory block; and
not performing the Nth programming of the first memory block and the second memory block in response to the conducting memory cell compaction.
8 . The method of claim 7 , wherein the memory cell compaction is conducted by moving the location of the (N−1)th-programming of the memory cell in the one memory block to a memory block having fewer open memory cells.
9 . The method of claim 8 , wherein the memory cell whose (N−1)th-programming location is moved is a memory cell existing on a word line of a same order in the first memory block and the second memory block.
10 . The method of claim 7 , wherein the open memory cell is an empty memory cell of a last word line that is (N−1)th programmed in the first memory block or the second memory block.
11 . The method of claim 10 , wherein, when the open memory cell does not exist, the memory cell compaction is not conducted.
12 . The method of claim 7 , wherein the storage device further comprises a third memory block and a storage controller of the storage device writes third data to the third memory block by performing programming of the third memory block N-times, and
the method further comprising:
detecting the open memory cell existing in the first memory block and the second memory block before the storage controller performs an Nth programming of the third memory block.
13 . A method for writing first data to a first memory block of a storage device, the method comprising:
programming the first memory block (N−1)-times to write first data to the first memory block, N being a positive integer greater than 1;
checking whether the first data is invalid data before an Nth programming of a first memory cell is performed; and
not performing the Nth programming of the first memory cell when the first data is the invalid data.
14 . The method of claim 13 , wherein the storage device comprises a buffer memory configured to store the first data,
the method further comprising:
checking whether the first data stored in the buffer memory is the invalid data.
15 . The method of claim 13 , further comprising:
performing address mapping by using a mapping table which stores mapping information between a first logical address of the first data and a first physical address of the first data; and
checking whether the first data in the mapping table is the invalid data.
16 . The method of claim 13 , wherein, when the first data is trimmed data, the first data is the invalid data.
17 . The method of claim 13 , wherein, when the first data is not mapped in a mapping table, the first data is the invalid data.
18 . The method of claim 13 , wherein second data is written to a second memory cell connected to a same word line as the first memory cell by performing programming of the second memory cell N-times, and
wherein, when the first data is the invalid data, the Nth programming of the first memory cell is not performed and the Nth programming of the second memory cell is performed to write the second data.
19 . The method of claim 18 , further comprising:
performing programming of a third memory cell of the storage device N-times,
wherein the third memory cell is connected to the same word line as the first memory cell and the second memory cell.