Electronic circuit with RRAM cells
An electronic circuit is provided that performs binary computation operations and includes word, bit and source lines, and memory cells organized in rows and columns. Each cell includes one pair of memristors and one pair of switches, each memristor being connected to a switch and linked to the same source line during each computation operation, each pair of memristors storing a binary value; the switches being linked to a word line and to a pair of complementary bit lines. The circuit includes a reading module that includes a logic unit for each column, each including an input terminal connected to a source line to receive a column value, the logic unit toggling between values, depending on a comparison of the column value with a toggle threshold value; and a modification unit for modifying a difference between the column and threshold values.
1 . An electronic circuit suitable for implementing computation operations each providing a binary output, the circuit comprising:
word lines;
pairs of complementary bit lines;
source lines;
a set of memory cells organized in a matrix including rows and columns, the memory cells of a same row being selectable by at least one word line, the memory cells of a same column being linked to a pair of complementary bit lines and at least one source line;
each memory cell having at least one pair of memristors and at least one pair of switches, each memristor of a respective memory cell being connected to a respective switch and linked to a same source line during each computation operation, each pair of memristors correspondingly storing a binary value presenting, correspondingly, first and second different resistance values; the switches being linked, for activation, to a respective word line and correspondingly linked to a pair of complementary bit lines, the two switches of a respective pair being linked to a same word line;
a reading module implemented during each computation operation, the reading module including:
a logic unit for each column, each logic unit comprising at least one input terminal connected to a respective source line, for receiving an input value called a column value, the logic unit being suitable for performing a logic operation which toggles between a low value and a high value depending on a comparison of the column value with a toggle threshold value, during the computation operation, the logic unit forming a logic inverter during the computation operation, and
a modification unit suitable for modifying, for at least one logic unit and according to the desired computation operation, a difference between the column value and the toggle threshold value.
2 . The electronic circuit according to claim 1 , wherein the modification unit is suitable for modifying the difference between the column value and the toggle value for a respective logic unit, by commanding a modification of the complementary voltages applied to the pair of complementary bit lines for the column associated with said logic unit.
3 . The electronic circuit according to claim 1 , wherein the modification unit is suitable for modifying the difference between the column value and the threshold value for a respective logic unit, by commanding a modification of the threshold value of said logic unit.
4 . The electronic circuit according to claim 3 , wherein said threshold value is modified by a change in the supply voltage of said logic unit and/or by a change in the bias voltage of a rear gate of at least one transistor of said logic unit.
5 . The electronic circuit according to claim 1 , wherein the modification unit is suitable for modifying, incrementally according to a predefined incrementation step, said difference between the column value and the toggle threshold value, for determining—among a plurality of predefined possible values—a resulting value corresponding to the voltage of the respective source line corresponding to said column value; the incrementation step depending on said plurality of possible values.
6 . The electronic circuit according to claim 5 , wherein the reading module further includes a storage unit for at least one column, each storage unit being suitable for storing the resulting value determined for the respective column, pending the determination of all the resulting values for a respective group of a plurality of columns.
7 . The electronic circuit according to claim 6 , wherein each storage unit preferentially including a bit register for storing said determined resulting value in binary form.
8 . The electronic circuit according to claim 5 , wherein the reading module further includes an extinction unit for each column, each extinction unit being suitable—after determining the resulting value for the respective column and pending determination of all the resulting values for a respective group—for commanding the application of a same voltage to the pair of complementary bit lines for the circulation of a substantially zero current in the source line of the respective column.
9 . The electronic circuit according to claim 1 , wherein each memory cell includes two pairs of memristors and two pairs of switches.
10 . The electronic circuit according to claim 9 , wherein a first pair of switches is linked to a first word line assigned to an input, and a second pair of switches, respectively, is linked to a second word line assigned to the inverse of said input; and wherein a first pair of memristors is associated with the first pair of switches and storing a binary value, and a second pair of memristors, respectively, being associated with the second pair of switches and storing the inverse of a same binary value.
11 . The electronic circuit according to claim 1 , wherein each memory cell includes only one pair of memristors and only one pair of switches, each pair of memristors correspondingly storing a synaptic weight.
12 . The electronic circuit according to claim 1 , wherein the logic operation performed by the logic unit is an inversion, and the associated computation operation is chosen from: a neural computation operation; an AND operation; an OR operation; a Majority operation.
13 . The electronic circuit according to claim 1 , wherein the value of the toggle threshold depends on the associated computation operation.
14 . The electronic circuit according to claim 13 , wherein when the associated computation operation is the AND operation or the OR operation, the value of the toggle threshold is at a voltage step from a voltage of a corresponding bit line, the corresponding voltage of the bit line being one of the voltages of the complementary bit lines for the AND operation and the other of the voltages complementary bit lines for the OR operation, the voltage step satisfying the following equation:
P
=
Δ
BL
OPD
+
1
where P represents the voltage step;
ΔBL represents the voltage differential between the voltage of the bit line and the voltage of the complementary bit line, and
OPD represents the number of operands to which the computation operation is applied.
15 . The electronic circuit according to claim 13 , wherein when the associated computation operation is the Majority operation, the value of the toggle threshold is a median value of the voltages of the complementary bit lines.
16 . The electronic circuit according to claim 1 , wherein the reading module further comprises a combination unit for at least one column, each combination unit being suitable for combining the results of logic operations performed successively by a respective logic unit, for implementing a combined logic operation.
17 . The electronic circuit according to claim 16 , wherein each combination unit includes a flip-flop connected to the output of the respective logic unit.
18 . The electronic circuit according to claim 16 , wherein the combined logic operation is chosen from the group consisting of: an exclusive OR operation and an exclusive NOR.
19 . The electronic circuit according to claim 1 , wherein the logic unit is a logic gate having an output and performing a Boolean function between a plurality of inputs, one input being the input terminal connected to the source line and the other input(s) being positioned in a neutral logic state during the computation operation, so that the logic unit behaves as an inverter between the input terminal connected to the source line and the output.
20 . The electronic circuit according to claim 1 , wherein each memory cell of a respective column comprises at least one pair of sub-cells, each sub-cell including a memristor and a switch, each memristor of a respective sub-cell being connected to a respective source line and switch, the memristors of each pair of sub-cells correspondingly storing a binary value by correspondingly presenting first and second different resistance values; the switches being linked, for the activation thereof, to a respective word line and correspondingly linked to a pair of complementary bit lines, the two switches of a respective pair of sub-cells being linked to the same word line; the two source lines associated with a respective pair of sub-cells being connected to each other via an auxiliary switch during each computation operation and then forming the same source line to which each memristor of a respective memory cell is linked during each computation operation.
21 . The electronic circuit according to claim 1 , wherein the electronic circuit is a neuromorphic circuit suitable for implementing a neural network with binary output, each memory cell being associated with a respective synaptic weight of a neuron, and the word lines being apt to receive input voltages during a neural computation.
22 . The electronic circuit according to claim 1 , comprising a first controller for selecting the memory cells of a row which are linked to the same word line, and comprising a second controller linked to the pairs of bit lines and used for applying different voltages to each pair bit line and symmetrical with respect to a middle voltage, the voltage applied to a bit line being either higher or lower than the voltage applied to the associated complementary bit line.
23 . The electronic circuit according to claim 1 , wherein the electronic circuit includes a plurality of distinct sets of memory cells suitable for operating in parallel.