Granted Patent B2

US 12,525,449 · App. 18/117,729 · Granted Jan 13, 2026

Inventors: Viljami Pore (Helsinki, FI); Werner Knaepen (Leuven, BE); Bert Jongbloed (Oud-Heverlee, BE); Dieter Pierreux (Dilbeek, BE); Steven R.A. Van Aerde (Tielt-Winge, BE); Suvi Haukka (Helsinki, FI); Atsuki Fukazawa (Tama, JP); Hideaki Fukuda (Hachioji, JP)

Assignee: ASM IP Holding B.V.

H01L21/0228C23C16/045C23C16/402C23C16/45534C23C16/45542H01J37/32009H01L21/02164H01L21/0217H01L21/02178H01L21/02183H01L21/02211H01L21/02219H01L21/02274H01L21/02299H01L21/76224H01J2237/3321H01J2237/334

Abstract

Claims (44)

1 . A semiconductor processing apparatus comprising:

one or more reaction chambers for accommodating a substrate provided with gaps created during manufacturing of a feature on the substrate;

a first source for a first reactant in gas communication via a first valve with one of the reaction chambers;

a second source for a second reactant in gas communication via a second valve with one of the reaction chambers; and

a third source for a third reactant, in gas communication via a third valve with one of the reaction chambers; wherein the apparatus comprises a controller operably connected to the first, second and third gas valves and configured and programmed to control:

introducing with the first valve a subsaturating first dose;

introducing with the second valve a saturating second dose; and

introducing with the third valve a third reactant to the substrate with a third dose, wherein the second reactant is a relatively high growth rate reactant in reaction with the third reactant;

wherein the second reactant is substantially blocked by the first reactant, and wherein the first reactant is introduced with a subsaturating first dose reaching a top area of the surface of the gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the gaps.

2 . The semiconductor processing apparatus of claim 1 , wherein the third source comprises H 2 O, O 2 , ozone, N 2 , H 2 , hydrazine, or ammonia.

3 . The semiconductor processing apparatus of claim 1 , wherein the controller is further configured and programmed to control: removing excess reactant and byproduct from the reaction chamber after each step of introducing a first, second and third reactant.

4 . The semiconductor processing apparatus of claim 1 , wherein the controller is further configured and programmed to control repeating:

introducing with the first valve the sub saturating first dose;

introducing with the second valve the saturating second dose; and

introducing with the third valve the third reactant to the substrate to fill the gaps.

5 . The semiconductor processing apparatus of claim 1 , wherein the third reactant comprises nitrogen, hydrogen, hydrazine, and/or ammonia.

6 . A semiconductor processing apparatus comprising:

one or more reaction chambers for accommodating a substrate provided with gaps created during manufacturing of a feature on the substrate;

a first source for a first reactant in gas communication via a first valve with one of the reaction chambers;

a second source for a second reactant in gas communication via a second valve with one of the reaction chambers; and

a third source for a third reactant, in gas communication via a third valve with one of the reaction chambers; wherein the apparatus comprises a controller operably connected to the first, second and third gas valves and configured and programmed to control:

introducing with the first valve a subsaturating first dose;

introducing with the second valve a saturating second dose; and

introducing with the third valve a third reactant to the substrate with a third dose, wherein the second reactant is a relatively high growth rate reactant in reaction with the third reactant;

wherein the first reactant is a low growth rate reactant in reaction with the third reactant.

7 . The semiconductor processing apparatus of claim 6 , wherein the low growth rate reactant comprises a silane.

8 . The semiconductor processing apparatus of claim 7 , wherein the low growth rate reactant comprises one or more reactants of a group of reactants comprising diiodomethylsilane, methoxy(dimethyl)octylsilane, alkylchlorosilanes, alkylalkoxysilanes, and alkylaminosilanes.

9 . A semiconductor processing apparatus comprising:

one or more reaction chambers for accommodating a substrate provided with gaps created during manufacturing of a feature on the substrate;

a first source for a first reactant in gas communication via a first valve with one of the reaction chambers;

a second source for a second reactant in gas communication via a second valve with one of the reaction chambers; and

a third source for a third reactant, in gas communication via a third valve with one of the reaction chambers; wherein the apparatus comprises a controller operably connected to the first, second and third gas valves and configured and programmed to control:

introducing with the first valve a subsaturating first dose;

introducing with the second valve a saturating second dose; and

introducing with the third valve a third reactant to the substrate with a third dose, wherein the second reactant is a relatively high growth rate reactant in reaction with the third reactant;

wherein the first reactant is a relatively no growth reactant whereby the first reactant is substantially removed from the surface in reaction with the third reactant.

10 . The semiconductor processing apparatus of claim 9 , wherein the relatively no growth reactant is an etch sensitive reactant and the third reactant causes etching of the first reactant so as to remove the first reactant from the surface.

11 . The semiconductor processing apparatus of claim 10 , wherein the first reactant comprises fluorine.

12 . The semiconductor processing apparatus of claim 11 , wherein the third reactant creates a plasma which removes fluorine from the etch sensitive reactant creating a fluorine plasma etching away the first reactant.

13 . The semiconductor processing apparatus of claim 10 , wherein the etch sensitive reactant comprises trimethoxy (3,3,3-tri-fluoropropyl) silane.

14 . The semiconductor processing apparatus of claim 10 , wherein the etch sensitive reactant comprises an amine group.

15 . The semiconductor processing apparatus of claim 10 , wherein the etch sensitive reactant comprises a di-isopropyl-amine group.

16 . The semiconductor processing apparatus of claim 10 , wherein the etch sensitive reactant comprises an alkane group.

17 . The semiconductor processing apparatus of claim 10 , wherein the etch sensitive reactant comprises octane.

Assignments (1)

Continuity (3)

References Cited (400)