Three dimensional semiconductor device and a method for manufacturing the same
A three dimensional semiconductor device includes first, second, third and fourth source/drain patterns sequentially stacked on a substrate, a contact structure on the first to fourth source/drain patterns and a contact line on the contact structure. The contact structure includes a first active contact on the first source/drain pattern, a second active contact on the second source/drain pattern, a third active contact on the third source/drain pattern, and a fourth active contact on the fourth source/drain pattern. A first vertical extension part of the first active contact is adjacent to one side of the contact structure, and a second vertical extension part of the second active contact is adjacent to the other side of the contact structure. A third vertical extension part of the third active contact is disposed between the first and second vertical extension parts and is closer to the first vertical extension part.
1 . A three dimensional semiconductor device comprising:
a first source/drain pattern, a second source/drain pattern, a third source/drain pattern, and a fourth source/drain pattern sequentially stacked on a substrate;
a contact structure on the first source/drain pattern, the second source/drain pattern, the third source/drain pattern, and the fourth source/drain pattern; and
a contact line on the contact structure,
wherein the contact structure includes a first active contact on the first source/drain pattern, a second active contact on the second source/drain pattern, a third active contact on the third source/drain pattern, and a fourth active contact on the fourth source/drain pattern,
wherein the first active contact includes a first horizontal extension part connected to the first source/drain pattern and a first vertical extension part extending from the first horizontal extension part to an uppermost portion of the contact structure,
wherein the second active contact includes a second horizontal extension part connected to the second source/drain pattern and a second vertical extension part extending from the second horizontal extension part to the uppermost portion of the contact structure,
wherein the third active contact includes a third horizontal extension part connected to the third source/drain pattern and a third vertical extension part extending from the third horizontal extension part to the uppermost portion of the contact structure,
wherein the fourth active contact includes a fourth horizontal extension part connected to the fourth source/drain pattern,
wherein the first vertical extension part is adjacent to a first side of the contact structure, and the second vertical extension part is adjacent to a second side of the contact structure,
wherein the third vertical extension part is arranged between the first vertical extension part and the second vertical extension part,
wherein the third vertical extension part is closer to the first vertical extension part than the second vertical extension part, and
wherein the second horizontal extension part includes an overlapping portion vertically overlapping with at least part of the third vertical extension part.
2 . The three dimensional semiconductor device of claim 1 , further comprising:
a first channel pattern, a second channel pattern, a third channel pattern, and a fourth channel pattern sequentially stacked on the substrate and respectively connected to the first source/drain pattern, the second source/drain pattern, the third source/drain pattern, and the fourth source/drain pattern; and
a gate structure on the first channel pattern, the second channel pattern, the third channel pattern, and the fourth channel pattern,
wherein the gate structure includes
a first gate electrode on the first channel pattern,
a second gate electrode on the second channel pattern,
a third gate electrode on the third channel pattern, and
a fourth gate electrode on the fourth channel pattern.
3 . The three dimensional semiconductor device of claim 2 ,
wherein the first channel pattern, the second channel pattern, the third channel pattern, and the fourth channel pattern include a plurality of semiconductor patterns that are stacked and spaced apart from one another, and
wherein each of the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode surrounds the plurality of semiconductor patterns.
4 . The three dimensional semiconductor device of claim 1 , wherein the fourth active contact is interposed between the second vertical extension part and the third vertical extension part.
5 . The three dimensional semiconductor device of claim 1 , comprising a via between a top surface of the first vertical extension part, the second vertical extension part, and the third vertical extension part and the contact line.
6 . The three dimensional semiconductor device of claim 1 , wherein the first vertical extension part, the second vertical extension part, the third vertical extension part, and the fourth horizontal extension part are sequentially stacked along the first source/drain pattern, the second source/drain pattern, the third source/drain pattern, and the fourth source/drain pattern, respectively.
7 . The three dimensional semiconductor device of claim 1 , wherein the fourth active contact excludes a fourth vertical extension part.
8 . The three dimensional semiconductor device of claim 1 , wherein at least one of the first source/drain pattern, the second source/drain pattern, the third source/drain pattern, and the fourth source/drain pattern has an N-type conductivity type, and
wherein others of the first source/drain pattern, the second source/drain pattern, the third source/drain pattern, and the fourth source/drain pattern have a P-type conductivity type.
9 . The three dimensional semiconductor device of claim 1 ,
wherein a first row, a second row, a third row, and a fourth row are sequentially defined in an extension direction of the contact structure,
wherein a top surface of the first vertical extension part is arranged in the first row,
wherein a top surface of the third vertical extension part is arranged in the second row,
wherein a top surface of the fourth horizontal extension part is arranged in the third row, and
wherein a top surface of the second vertical extension part is arranged in the fourth row.
10 . A three dimensional semiconductor device comprising:
a first source/drain pattern, a second source/drain pattern, a third source/drain pattern, and a fourth source/drain pattern sequentially stacked on a substrate;
a contact structure on the first source/drain pattern, the second source/drain pattern, the third source/drain pattern, and the fourth source/drain pattern; and
a contact line on the contact structure,
wherein the contact structure includes
a first active contact connected to the first source/drain pattern,
a second active contact connected to the second source/drain pattern,
a third active contact connected to the third source/drain pattern, and
a fourth active contact connected to the fourth source/drain pattern,
wherein the first active contact, the second active contact, the third active contact, and the fourth active contact are sequentially stacked along the first source/drain pattern, the second source/drain pattern, the third source/drain pattern, and the fourth source/drain pattern, respectively,
wherein the first active contact, the second active contact, and the third active contact include a first vertical extension part, a second vertical extension part, and a third vertical extension part extending to an uppermost portion of the contact structure, respectively,
wherein the second vertical extension part is arranged opposite to the first vertical extension part with the stacked first source/drain pattern, second source/drain pattern, third source/drain pattern, and fourth source/drain pattern interposed therebetween,
wherein the third vertical extension part is arranged opposite to the second vertical extension part with the stacked first source/drain pattern, second source/drain pattern, third source/drain pattern, and fourth source/drain pattern interposed between the third vertical extension part and the second vertical extension part, and
wherein the second active contact includes an overlapping portion vertically overlapping with at least a part of the third active contact.
11 . The three dimensional semiconductor device of claim 10 , comprising:
a first channel pattern, a second channel pattern, a third channel pattern, and a fourth channel pattern sequentially stacked on the substrate and configured to be connected to the first source/drain pattern, the second source/drain pattern, the third source/drain pattern, and the fourth source/drain pattern, respectively; and
a gate structure on the first channel pattern, the second channel pattern, the third channel pattern, and the fourth channel pattern,
wherein the gate structure includes
a first gate electrode on the first channel pattern,
a second gate electrode on the second channel pattern,
a third gate electrode on the third channel pattern, and
a fourth gate electrode on the fourth channel pattern.
12 . The three dimensional semiconductor device of claim 10 , wherein the fourth active contact is interposed between the second vertical extension part and the third vertical extension part.
13 . The three dimensional semiconductor device of claim 10 , comprising a via between a top surface of the first vertical extension part, the second vertical extension part, and the third vertical extension part and the contact line.
14 . The three dimensional semiconductor device of claim 10 ,
wherein at least one of the first source/drain pattern, the second source/drain pattern, the third source/drain pattern, and the fourth source/drain pattern has an N-type conductivity type, and
wherein others of the first source/drain pattern, the second source/drain pattern, the third source/drain pattern, and the fourth source/drain pattern have a P-type conductivity type.
15 . A three dimensional semiconductor device comprising:
a first source/drain pattern, a second source/drain pattern, a third source/drain pattern, and a fourth source/drain pattern sequentially stacked on a substrate;
a contact structure on the first source/drain pattern, the second source/drain pattern, the third source/drain pattern, and the fourth source/drain pattern; and
a first contact line and a second contact line on the contact structure,
wherein the contact structure includes
a first active contact connected to the first source/drain pattern,
a second active contact connected to the second source/drain pattern,
a third active contact connected to the third source/drain pattern, and
fourth active contact connected to the fourth source/drain pattern,
wherein the first active contact, the second active contact, the third active contact, and the fourth active contact are sequentially stacked along the first source/drain pattern, the second source/drain pattern, the third source/drain pattern, and the fourth source/drain pattern, respectively,
wherein the first active contact, the second active contact, and the third active contact include a first vertical extension part, a second vertical extension part, and a third vertical extension part extending to an uppermost portion of the contact structure, respectively,
wherein the first vertical extension part and the third vertical extension part adjacent to each other are electrically connected to each other by the first contact line, and
wherein the second vertical extension part and the fourth active contact adjacent to each other are electrically connected to each other by the second contact line.
16 . The three dimensional semiconductor device of claim 15 ,
wherein the first vertical extension part is adjacent to one side of the contact structure,
wherein the second vertical extension part is adjacent to another side of the contact structure, and
wherein the third vertical extension part is between the first vertical extension part and the second vertical extension part, and is closer to the first vertical extension part than to the second vertical extension part.
17 . The three dimensional semiconductor device of claim 15 , wherein the fourth active contact is interposed between the second vertical extension part and the third vertical extension part.
18 . The three dimensional semiconductor device of claim 15 , comprising:
a first channel pattern, a second channel pattern, a third channel pattern, and a fourth channel pattern sequentially stacked on the substrate, and connected to the first source/drain pattern, the second source/drain pattern, the third source/drain pattern, and the fourth source/drain pattern, respectively; and
a gate structure on the first source/drain pattern, the second source/drain pattern, the third source/drain pattern, and the fourth source/drain pattern,
wherein the gate structure includes
a first gate electrode on the first channel pattern,
a second gate electrode on the second channel pattern,
a third gate electrode on the third channel pattern, and
a fourth gate electrode on the fourth channel pattern.
19 . The three dimensional semiconductor device of claim 18 , wherein the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are separated from one another by a separation structure.