Power reduction in finFET structures
The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.
1 . A structure, comprising:
a substrate;
a first semiconductor fin structure and a second semiconductor fin structure on the substrate, wherein the first and second semiconductor fin structures are spaced apart by a first dielectric layer;
a first insulating fin structure between the first and second semiconductor fin structures;
a second insulating fin structure adjacent to the first semiconductor fin structure, wherein the first semiconductor fin structure is between the first and second insulating fin structures;
a third insulating fin structure adjacent to the second semiconductor fin structure, wherein the second semiconductor fin structure is between the first and third insulating fin structures; and
a second dielectric layer on top portions of the first semiconductor fin structure, the second semiconductor fin structure, the first insulating fin structure, the second insulating fin structure, and the third insulating fin structure.
2 . The structure of claim 1 , further comprising:
a first epitaxial stack on the first semiconductor fin structure; and
a second epitaxial stack on the second semiconductor fin structure, wherein the second epitaxial stack is taller than the first epitaxial stack.
3 . The structure of claim 2 , wherein the second epitaxial stack is wider than the first epitaxial stack.
4 . The structure of claim 2 , wherein the second epitaxial stack is bounded by the first and third insulating fin structures.
5 . The structure of claim 2 , wherein a first distance between a top surface of the first epitaxial stack and a top surface of the first dielectric layer is greater than a second distance between a top surface of the second epitaxial stack and the top surface of the first dielectric layer.
6 . The structure of claim 2 , further comprising a spacer on a side surface of first semiconductor fin structure and under the first epitaxial stack.
7 . The structure of claim 2 , further comprising first and second contacts on the first and second epitaxial stacks, respectively.
8 . The structure of claim 1 , wherein the first, second, and third insulating fin structures comprise one or more of silicon oxy-carbon nitride (SiOCN), silicon oxy-carbide (SiOC), hafnium oxide (HfO 2 ), and zirconium oxide (ZrO 2 ).
9 . A structure, comprising:
a substrate;
a first semiconductor fin structure and a second semiconductor fin structure on the substrate;
a first dielectric layer between the first and second semiconductor fin structures;
an epitaxial stack on the first semiconductor fin structure, wherein a distance between a bottom of the epitaxial stack and a top surface of the first dielectric layer is greater than zero;
an insulating fin structure having a lower portion embedded in the dielectric layer; and
a second dielectric layer on the first and second semiconductor fin structures and in contact with a top surface of the insulating fin structure.
10 . The structure of claim 9 , wherein the second dielectric layer comprises a first portion on a side surface of the insulating fin structure and a second portion on a side surface of the epitaxial stack, and wherein a first side surface of the first portion opposes a second side surface of the second portion.
11 . The structure of claim 9 , further comprising a spacer on a side surface of the first semiconductor fin structure and in contact with the bottom of the epitaxial stack.
12 . The structure of claim 11 , wherein the second dielectric layer comprises a first portion on a side surface of the insulating fin structure and a second portion on a side surface of the spacer, and wherein a first side surface of the first portion opposes a second side surface of the second portion.
13 . The structure of claim 9 , further comprising an other epitaxial stack on the second semiconductor fin structure, wherein a bottom of the other epitaxial stack is in contact with a top surface of the first dielectric layer.
14 . The structure of claim 13 , wherein a first height of a side surface of the epitaxial stack is less than a second height of a side surface of the other epitaxial stack.
15 . The structure of claim 13 , wherein a first distance between a top surface of the epitaxial stack and a top surface of the first semiconductor fin structure is greater than a second distance between a top surface of the other epitaxial stack and a top surface of the second semiconductor fin structure.
16 . A structure, comprising:
first and second semiconductor fin structures on a substrate;
a dielectric layer on the substrate and between the first and second semiconductor fin structures;
a spacer on the dielectric layer and abutting the first semiconductor fin structure;
a first epitaxial stack on the first semiconductor fin structure and the spacer;
a second epitaxial stack on the second semiconductor fin structure and the dielectric layer; and
an insulating structure in contact with the second epitaxial stack.
17 . The structure of claim 16 , wherein a height of the second epitaxial stack is greater than a height of the first epitaxial stack, and wherein a width of the second epitaxial stack is greater than a width of the first epitaxial stack.
18 . The structure of claim 16 , further comprising an interlayer dielectric (ILD) between the first epitaxial stack and the insulating structure.
19 . The structure of claim 18 , further comprising another dielectric layer having a portion between the first epitaxial stack and the ILD.
20 . The structure of claim 16 , wherein the insulating structure comprises an insulating fin structure between the first and second semiconductor fin structures.