IP Library › Granted Patent US 12,530,270
Granted Patent B2
US 12,530,270 · App. 17/903,959 · Granted Jan 20, 2026

Frequency adjustment for processors

Inventors: Sreedhar Narayanaswamy (Sunnyvale, CA); Benjamin D. Faulkner (Los Altos Hills, CA)
Assignee: NVIDIA Corporation
G06F11/1629
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Quick Facts
Patent No.
US 12,530,270
App. No.
17/903,959
Granted
Jan 20, 2026
Kind
B2
Abstract

Apparatuses, systems, and techniques adjust a frequency at which a processor operates. In at least one embodiment, a frequency at which a processor operates is adjusted based, at least in part, on different cores of the processor performing one or more identical instructions.

Claims (22)

1 . A processor, comprising:

one or more circuits to adjust a frequency at which a processor operates based, at least in part, on different cores of the processor performing one or more identical instructions, adjusting the frequency at which the processor operates performed by an error detection mode associated with the one or more circuits, wherein the error detection mode is performed by a firmware engine of the processor that causes the different cores to execute the one or more identical instructions and adjusts the frequency at which the processor operates.

2 . The processor according to claim 1 , wherein adjusting the frequency at which the processor operates comprises increasing the frequency at which the processor operates based, at least in part, on the different cores of the processor performing the one or more identical instructions.

3 . The processor according to claim 1 , wherein adjusting the frequency at which the processor operates comprises increasing a frequency at which at least one of the different cores operates based, at least in part, on the different cores of the processor performing the one or more identical instructions.

4 . The processor according to claim 1 , wherein adjusting the frequency at which the processor operates based, at least in part, on the different cores of the processor performing the one or more identical instructions comprises activating the error detection mode in firmware of the one or more circuits.

5 . The processor according to claim 1 , wherein the error detection mode compares output data of the different cores to determine if the output data from the different cores match.

6 . The processor according to claim 1 , wherein the one or more circuits are further to perform an additional adjustment of the frequency at which the processor operates based, at least in part, on comparing output data of the different cores.

7 . A method, comprising:

adjusting a frequency at which a processor operates based, at least in part, on different cores of the processor performing one or more identical instructions, adjusting the frequency further based, at least in part, on performing an error detection mode, associated with the processor, to allocate at least one core of the different cores, wherein the error detection mode is performed by a firmware engine of the processor.

8 . The method of claim 7 , wherein adjusting the frequency at which the processor operates comprises increasing the frequency at which the processor operates based, at least in part, on the different cores of the processor performing the one or more identical instructions.

9 . The method of claim 7 , wherein adjusting the frequency at which the processor operates comprises increasing a frequency at which at least one of the different cores operates based, at least in part, on the different cores of the processor performing the one or more identical instructions.

10 . The method of claim 7 , wherein adjusting the frequency at which the processor operates based, at least in part, on the different cores of the processor performing the one or more identical instructions comprises activating, by the firmware engine, the error detection mode that causes the different cores of the processor to perform the one or more identical instructions.

11 . The method of claim 7 , wherein adjusting the frequency at which the processor operates based, at least in part, on the different cores of the processor performing the one or more identical instructions comprises activating the error detection mode, by the firmware engine, that compares output data of the different cores to determine if the output data from the different cores match.

12 . The method of claim 7 , further comprising performing an additional adjustment of the frequency at which the processor operates based, at least in part, on comparing output data of the different cores.

13 . The method of claim 7 , further comprising enabling the error detection mode to cause the different cores of the processor to perform the one or more identical instructions.

14 . A system comprising:

one or more processors to adjust a frequency at which a processor operates based, at least in part, on different cores of the processor performing one or more identical instructions, adjusting the frequency further based, at least in part, on performing an error detection mode, associated with the one or more processors, to allocate at least one core of the different cores, wherein the error detection mode is performed by a firmware engine of the processor that causes adjusting the frequency at which the processor operates.

15 . The system of claim 14 , wherein adjusting the frequency at which the processor operates comprises increasing the frequency at which the processor operates based, at least in part, on the different cores of the processor performing the one or more identical instructions.

16 . The system of claim 14 , wherein adjusting the frequency at which the processor operates comprises increasing a frequency at which at least one of the different cores operates based, at least in part, on the different cores of the processor performing the one or more identical instructions.

17 . The system of claim 14 , wherein adjusting the frequency at which the processor operates based, at least in part, on the different cores of the processor performing the one or more identical instructions comprises activating, by the firmware engine, the error detection mode.

18 . The system of claim 14 , wherein adjusting the frequency at which the processor operates based, at least in part, on the different cores of the processor performing the one or more identical instructions comprises activating, by the firmware engine, the error detection mode that compares output data of the different cores to determine if the output data from the different cores match.

19 . The system of claim 14 , wherein the one or more processors are further to cause an additional adjustment of the frequency at which the processor operates based, at least in part, on comparing output data of the different cores.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2022
From: NARAYANASWAMY, SREEDHAR; FAULKNER, BENJAMIN D.
To: NVIDIA CORPORATION
Reel/Frame 061188/0604 →
Continuity (1)
Related Publication 20240095133A1 · Mar 21, 2024
References Cited (7)
US 7412353B2 · Borkar · 2008 [cited by examiner]
US 10429919B2 · Rotem · 2019 [cited by examiner]
US 20050240810A1 · Safford · 2005 [cited by examiner]
US 20120233506A1 · Kameda · 2012 [cited by examiner]
US 20210081016A1 · Hovis · 2021 [cited by examiner]
EP 3493062A2 · 2019 [cited by examiner]
IEEE “IEEE Standard for Floating-Point Arithmetic”, Microprocessor Standards Committee of the IEEE Computer Society, IEEE Std 754-2008, dated Jun. 12, 2008, 70 pages. [cited by applicant]