IP Library › Granted Patent US 12,531,484
Granted Patent B2
US 12,531,484 · App. 18/118,729 · Granted Jan 20, 2026

Power supply circuit for preventing internal breakdown

Inventor: Chen kong Teh (Ota Tokyo, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H02M3/158H02H11/003H02M1/08
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Quick Facts
Patent No.
US 12,531,484
App. No.
18/118,729
Granted
Jan 20, 2026
Kind
B2
Abstract

A power supply circuit of an embodiment includes a first transistor including a source connected to an input terminal, and a gate connected to a first node; a second transistor including a drain connected to a drain of the first transistor, and a source connected to an output terminal; a third transistor including a source connected to the input terminal, a drain connected to the first node, and a gate connected to a second node; and a Zener diode including an anode connected to the input terminal, and a cathode connected to the second node.

Claims (15)

1 . A power supply circuit comprising:

a first transistor including a source connected to an input terminal, and a gate connected to a first node;

a second transistor including a drain connected to a drain of the first transistor, and a source connected to an output terminal;

a third transistor including a source connected to the input terminal, a drain connected to the first node, and a gate connected to a second node;

a Zener diode including an anode connected to the input terminal, and a cathode connected to the second node; and

a fourth transistor and a fifth transistor that are connected between the second node and a reference potential, the fourth transistor and the fifth transistor being NMOS transistors including gates and sources connected in common.

2 . The power supply circuit according to claim 1 , further comprising a capacitor connected in parallel with the fourth transistor and the fifth transistor.

3 . The power supply circuit according to claim 1 , further comprising a sixth transistor connected between the reference potential and the output terminal.

4 . The power supply circuit according to claim 1 , further comprising a seventh transistor and an eighth transistor that are connected between the input terminal and the reference potential and include gates and drains connected in common to a reference potential of a substrate.

5 . The power supply circuit according to claim 1 , further comprising a gate controller, the gate controller being configured to output a gate control signal to the gate of the first transistor and a gate of the second transistor.

6 . The power supply circuit according to claim 5 , wherein the gate controller is configured to output the gate control signal to the gate of the first transistor via the first node.

7 . The power supply circuit according to claim 1 , further comprising a resistor, the resistor including one end connected to the second node, and another end connected to a reference potential.

8 . The power supply circuit according to claim 1 , further comprising a plurality of diodes connected in a forward direction between the input terminal and the second node.

9 . The power supply circuit according to claim 1 , further comprising a resistor, the resistor including one end connected to the second node, and another end connected to the output terminal.

10 . The power supply circuit according to claim 1 , further comprising a resistor, the resistor including one end connected to the second node, and another end connected to a third node between the first transistor and the second transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2023
From: TEH, CHEN KONG
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 062932/0504 →
Priority Claims (1)
JP 2022-153010 · Sep 26, 2022 · national
Continuity (1)
Related Publication 20240106329A1 · Mar 28, 2024
References Cited (15)
US 5410441A · Allman · 1995 [cited by examiner]
US 6304422B1 · Sander · 2001 [cited by examiner]
US 9312688B1 · Farina · 2016 [cited by examiner]
US 20200028503A1 · Soma · 2020 [cited by applicant]
US 20200067501A1 · Hayashi · 2020 [cited by applicant]
US 20210184667A1 · Hayashi et al. · 2021 [cited by applicant]
CN 106452372A · 2017 [cited by examiner]
CN 207588698U · 2018 [cited by examiner]
JP 2002512498A · 2002 [cited by applicant]
JP 2020014356A · 2020 [cited by applicant]
JP 2021097324A · 2021 [cited by applicant]
JP 2021158861A · 2021 [cited by applicant]
JP 7002423B2 · 2022 [cited by applicant]
Demo Manual DC2062A, “LT4363-1/LT4363-2 12V Systems ISO-7637-2 Surge Stopper,” Linear Technology, 2013 (Year: 2013). [cited by examiner]
Office Action mailed Aug. 26, 2025 in corresponding Japanese Patent Application No. 2022-153010 with English translation, 7 pages. [cited by applicant]