Semiconductor device including capacitor block
A semiconductor device includes a first capacitor block including a first conductive plate, and first lower electrodes on the first conductive plate, a second capacitor block including a second conductive plate spaced apart from the first conductive plate, and second lower electrodes on the second conductive plate, a first edge capacitor block including first edge electrodes on the first conductive plate and surrounding the first capacitor block, a second edge capacitor block including a second edge electrodes on the second conductive plate and surrounding the second capacitor block and a first electrode support which supports the first lower electrodes, the second lower electrodes, the first edge electrodes, and the second edge electrodes. A first penetration pattern penetrates the first electrode support, is over the first lower electrodes and the second lower electrodes, and is not over the first edge electrodes and the second edge electrodes.
1 . A semiconductor device comprising:
a first capacitor block including a first conductive plate on a substrate, and a plurality of first lower electrodes on the first conductive plate;
a second capacitor block including a second conductive plate spaced apart from the first conductive plate, and a plurality of second lower electrodes on the second conductive plate;
a separation block including a separation insulating film between the first conductive plate and the second conductive plate, and a plurality of dummy lower electrodes on the separation insulating film; and
a first electrode support supporting the plurality of first lower electrodes, the plurality of second lower electrodes, and the plurality of dummy lower electrodes.
2 . The semiconductor device of claim 1 , further comprising:
a first edge capacitor block including a plurality of first edge electrodes on the first conductive plate surrounding the first capacitor block,
wherein the first electrode support includes a first penetration pattern that penetrates the first electrode support, and
the first penetration pattern is over the plurality of first lower electrodes and is not over the plurality of first edge electrodes.
3 . The semiconductor device of claim 2 , further comprising:
a second edge capacitor block including a plurality of second edge electrodes on the second conductive plate surrounding the second capacitor block,
wherein the first penetration pattern is over the plurality of second lower electrodes and is not over the plurality of second edge electrodes.
4 . The semiconductor device of claim 1 , wherein the first electrode support includes a first penetration pattern penetrating the first electrode support and the first penetration pattern over the plurality of first lower electrodes and the plurality of second lower electrodes, and
the first penetration pattern is not over the plurality of dummy lower electrodes.
5 . The semiconductor device of claim 1 , further comprising:
a first edge capacitor block including a plurality of first edge electrodes on the first conductive plate surrounding the first capacitor block; and
a second edge capacitor block including a plurality of second edge electrodes on the second conductive plate surrounding the second capacitor block,
wherein the first electrode support includes a first penetration pattern penetrating the first electrode support, and the first penetration pattern is over the plurality of first lower electrodes and the plurality of second lower electrodes,
the first capacitor block includes a first surface facing the separation block, and the second capacitor block includes a second surface facing the separation block,
the first penetration pattern is over the plurality of first edge electrodes, the plurality of second edge electrodes, and the plurality of dummy lower electrodes between the first surface of the first capacitor block and the second surface of the second capacitor block,
the first penetration pattern is not over the plurality of first edge electrodes in the first edge capacitor block other than the plurality of first edge electrodes in the first edge capacitor block facing the first surface of the first capacitor block, and
the first penetration pattern is not over the plurality of second edge electrodes in the second edge capacitor block other than the plurality of second edge electrodes in the second edge capacitor block facing the second surface of the second capacitor block.
6 . The semiconductor device of claim 1 , further comprising:
a capacitor dielectric film extending along profiles of the plurality of first lower electrodes, the plurality of second lower electrodes, the plurality of dummy lower electrodes, upper surfaces of the first electrode support, and lower surfaces of the first electrode support; and
an upper electrode on the capacitor dielectric film.
7 . The semiconductor device of claim 1 , further comprising:
a second electrode support supporting the plurality of first lower electrodes, the plurality of second lower electrodes, and the plurality of dummy lower electrodes,
wherein
the second electrode support is between the first conductive plate and the first electrode support,
the second electrode support is further between the second conductive plate and the first electrode support, and
the second electrode support is further between the separation insulating film; and the first electrode support.
8 . The semiconductor device of claim 1 , wherein uppermost surfaces of the plurality of first lower electrodes, uppermost surfaces of the plurality of second lower electrodes, and uppermost surfaces of the plurality of dummy lower electrodes are coplanar with an uppermost surface of the first electrode support.
9 . The semiconductor device of claim 1 , further comprising:
a first contact connected to the first conductive plate, and the first contact spaced apart from the plurality of first lower electrodes; and
a second contact connected to the second conductive plate, and the second contact spaced apart from the plurality of second lower electrodes.
10 . The semiconductor device of claim 1 , wherein the plurality of first lower electrodes, the plurality of second lower electrodes, and the plurality of dummy lower electrodes have a pillar shape extending in a thickness direction of the substrate.
11 . The semiconductor device of claim 1 , wherein
a first interval is between a first lower electrode closest to the separation block and a first dummy lower electrode of the plurality of dummy lower electrodes,
a second interval is between a second lower electrode closest to the separation block and a second dummy lower electrode of the plurality of dummy lower electrodes, and
the first interval is a same interval as the second interval.
12 . A semiconductor device comprising:
a first capacitor block including a first conductive plate on a substrate, and a plurality of first lower electrodes on the first conductive plate;
a second capacitor block including a second conductive plate spaced apart from the first conductive plate, and a plurality of second lower electrodes on the second conductive plate;
a first edge capacitor block including a plurality of first edge electrodes on the first conductive plate surrounding the first capacitor block;
a second edge capacitor block including a plurality of second edge electrodes on the second conductive plate surrounding the second capacitor block; and
a first electrode support supporting the plurality of first lower electrodes, the plurality of second lower electrodes, the plurality of first edge electrodes, and the plurality of second edge electrodes,
wherein the first electrode support includes
a first penetration pattern penetrating the first electrode support, and
the first penetration pattern is over the plurality of first lower electrodes and the plurality of second lower electrodes, and
the first penetration pattern is not over the plurality of first edge electrodes and the plurality of second edge electrodes.
13 . The semiconductor device of claim 12 , further comprising:
a separation block between the first capacitor block and the second capacitor block including a separation insulating film between the first conductive plate and the second conductive plate, and
a plurality of dummy lower electrodes on the separation insulating film.
14 . The semiconductor device of claim 13 , wherein the first penetration pattern is not over the plurality of dummy lower electrodes.
15 . The semiconductor device of claim 13 , wherein
a first distance is between a first edge electrode of the plurality of first edge electrodes and a first dummy lower electrode of the plurality of dummy lower electrodes adjacent to the first edge electrode,
a second distance is between the first dummy lower electrode of the plurality of dummy lower electrodes and a second dummy lower electrode of the plurality of dummy lower electrodes adjacent to the first dummy lower electrode,
a third distance is between the second dummy lower electrode of the plurality of dummy lower electrodes and a second edge electrode of the plurality of second edge electrodes adjacent to the second dummy lower electrode, and
the first distance, the second distance, and the third distance are all a same distance.
16 . The semiconductor device of claim 12 , further comprising:
a capacitor dielectric film extending along profiles of the plurality of first lower electrodes, profiles of the plurality of second lower electrodes, profiles of the plurality of first edge electrodes, profiles of the plurality of second edge electrodes, upper surfaces of the first electrode support, and lower surfaces of the first electrode support; and
an upper electrode on the capacitor dielectric film.
17 . The semiconductor device of claim 16 , further comprising:
an etching stop film between the first conductive plate and the capacitor dielectric film, and
the etching stop film is further between the second conductive plate, and the capacitor dielectric film.
18 . A semiconductor device comprising:
a first capacitor block including a first conductive plate on a substrate, and a plurality of first lower electrodes on the first conductive plate;
a second capacitor block including a second conductive plate spaced apart from the first conductive plate, and a plurality of second lower electrodes on the second conductive plate;
a first edge capacitor block including a plurality of first edge electrodes on the first conductive plate surrounding the first capacitor block;
a second edge capacitor block including a plurality of second edge electrodes on the second conductive plate surrounding the second capacitor block;
a separation block including a separation insulating film between the first conductive plate and the second conductive plate, and the separation block including a plurality of dummy lower electrodes on the separation insulating film;
a first electrode support supporting the plurality of first lower electrodes, the plurality of second lower electrodes, the plurality of first edge electrodes, the plurality of second edge electrodes, and the plurality of dummy lower electrodes, and
the first electrode support including a first penetration pattern; and
a second electrode support supporting the plurality of first lower electrodes, the plurality of second lower electrodes, the plurality of first edge electrodes, the plurality of second edge electrodes, and the plurality of dummy lower electrodes,
the second electrode support including a second penetration pattern completely overlapping the first penetration pattern, and
the second electrode support is between the substrate and the first electrode support,
wherein the first penetration pattern is over the plurality of first lower electrodes and the plurality of second lower electrodes, and
the first penetration pattern is not over the plurality of first edge electrodes, the plurality of second edge electrodes, and the plurality of dummy lower electrodes.
19 . The semiconductor device of claim 18 , wherein uppermost surfaces of each of the plurality of first lower electrodes, the plurality of second lower electrodes, the plurality of first edge electrodes, the plurality of second edge electrodes, and the plurality of dummy lower electrodes are coplanar with an uppermost surface of the first electrode support.
20 . The semiconductor device of claim 18 , further comprising:
an etching stop film between the plurality of first lower electrodes and the plurality of dummy lower electrodes,
the etching stop film is further between the plurality of second lower electrodes and the plurality of dummy lower electrodes,
the etching stop film is further between the plurality of first edge electrodes and the plurality of dummy lower electrodes,
the etching stop film is further between the plurality of second edge electrodes, and the plurality of dummy lower electrodes, and
the etching stop film on the first conductive plate, the second conductive plate, and the separation insulating film;
a capacitor dielectric film extending along profiles of the plurality of first lower electrodes, the plurality of second lower electrodes, the plurality of first edge electrodes, the plurality of second edge electrodes, the plurality of dummy lower electrodes, upper surfaces of the first electrode support, lower surfaces of the first electrode support, upper surfaces of the second electrode support, and lower surfaces of the second electrode support, and
the capacitor dielectric film is on the etching stop film; and
an upper electrode on the capacitor dielectric film,
wherein the upper electrode extends from an uppermost surface of the capacitor dielectric film toward the substrate in the first capacitor block and the second capacitor block, and
the upper electrode does not extend from the uppermost surface of the capacitor dielectric film toward the substrate, in the first edge capacitor block and the second edge capacitor block.