Semiconductor device and electronic device
A semiconductor device with low power consumption is provided. The semiconductor device includes a first layer and a second layer. The first layer includes a first cell and a first to a third circuit, and the second layer includes a second cell and a fourth and a fifth circuit. The first, second, and fourth circuits each have a function of converting digital data into analog current. The first cell calculates a product of a value from the first current and a value from the second circuit and inputs a calculation result into a third circuit as current. The third circuit generates analog current from the input current. The second cell calculates a product of a value from the third circuit and a value from the fourth circuit and inputs a calculation result into the fifth circuit as current. The fifth circuit generates analog current from the input current.
1 . A semiconductor device comprising:
a first layer comprising a first cell, a first circuit, a second circuit, and a third circuit; and
a second layer comprising a second cell, a fourth circuit, and a fifth circuit,
wherein the first layer is located below the second layer,
wherein the first cell comprises a first transistor,
wherein the second cell comprises a second transistor,
wherein the first circuit is configured to convert a first data that is a digital data into a first analog current and configured to input the first analog current into the first cell,
wherein the second circuit is configured to convert a second data that is a digital data into a second analog current and configured to input the second analog current into the first cell,
wherein the fourth circuit is configured to convert a third data that is a digital data into a third analog current,
wherein the first cell is configured to retain a first potential corresponding to the first analog current at a gate of the first transistor and configured to set a current flowing between a source and a drain of the first transistor to a first current corresponding to the first potential,
wherein the second cell is configured to retain a third potential corresponding to the third analog current at a gate of the second transistor and configured to set a current flowing between a source and a drain of the second transistor to a third current corresponding to the third potential,
wherein the second circuit is configured to change the first potential retained in the first cell into a second potential by inputting the second analog current into the first cell,
wherein the first cell is configured to change the first current flowing between the source and the drain of the first transistor into a second current in accordance with the change of the first potential into the second potential,
wherein the third circuit is configured to generate a fourth analog current corresponding to the second current and configured to input the fourth analog current into the second cell, so that the third potential retained in the second cell is changed into a fourth potential,
wherein the second cell is configured to change the third current flowing between the source and the drain of the second transistor into a fourth current in accordance with the change of the third potential into the fourth potential, and
wherein the fifth circuit is configured to generate a fifth analog current corresponding to the fourth current.
2 . The semiconductor device according to claim 1 ,
wherein each of the first transistor and the second transistor comprises an oxide semiconductor in a channel formation region,
wherein the oxide semiconductor comprises at least one of indium, zinc, and an element M, and
wherein the element M is at least one of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony.
3 . The semiconductor device according to claim 2 ,
wherein an amount of each of the first current and the second current is an amount of current flowing when the first transistor operates in a subthreshold region, and
wherein an amount of each of the third current and the fourth current is an amount of current flowing when the second transistor operates in a subthreshold region.
4 . A semiconductor device comprising:
a first layer comprising a first cell, a first circuit, and a third circuit;
a second layer comprising a second cell, a fourth circuit, and a fifth circuit; and
a third layer comprising an optical sensor,
wherein the third layer is located above the first layer,
wherein the first layer is located above the second layer,
wherein the first cell comprises a first transistor,
wherein the second cell comprises a second transistor,
wherein the first circuit is configured to convert a first data that is a digital data into a first analog current and configured to input the first analog current into the first cell,
wherein the optical sensor is configured to generate a second analog current when receiving light and configured to input the second analog current into the first cell,
wherein the fourth circuit is configured to convert a third data that is a digital data into a third analog current,
wherein the first cell is configured to retain a first potential corresponding to the first analog current at a gate of the first transistor and configured to set a current flowing between a source and a drain of the first transistor to a first current corresponding to the first potential,
wherein the second cell is configured to retain a third potential corresponding to the third analog current at a gate of the second transistor and configured to set a current flowing between a source and a drain of the second transistor to a third current corresponding to the third potential,
wherein the optical sensor is configured to change the first potential retained in the first cell into a second potential by inputting the second analog current into the first cell,
wherein the first cell is configured to change the first current flowing between the source and the drain of the first transistor into a second current in accordance with the change of the first potential into the second potential,
wherein the third circuit is configured to generate a fourth analog current corresponding to the second current and configured to input the fourth analog current into the second cell, so that the third potential retained in the second cell is changed into a fourth potential,
wherein the second cell is configured to change the third current flowing between the source and the drain of the second transistor into a fourth current in accordance with the change of the third potential into the fourth potential, and
wherein the fifth circuit is configured to generate a fifth analog current corresponding to the fourth current.
5 . The semiconductor device according to claim 4 ,
wherein each of the first transistor and the second transistor comprises an oxide semiconductor in a channel formation region,
wherein the oxide semiconductor comprises at least one of indium, zinc, and an element M, and
wherein the element M is at least one of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony.
6 . The semiconductor device according to claim 5 ,
wherein an amount of each of the first current and the second current is an amount of current flowing when the first transistor operates in a subthreshold region, and
wherein an amount of each of the third current and the fourth current is an amount of current flowing when the second transistor operates in a subthreshold region.