Stacked capacitors for semiconductor devices and associated systems and methods
Semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having an inner surface, a die stack carried by the inner surface, and a stacked capacitor device carried by the inner surface adjacent to the die stack. The die stack can include one or more semiconductor dies, each of which can be electrically coupled to the inner surface by one or more bond wires and/or solder structures. The stacked capacitor device can include a first capacitor having a lower surface attached to the inner surface of the package substrate, a interposer having a first side attached to an upper surface of the first capacitor, and a second capacitor attached to a second side of the interposer opposite the first side.
1 . A semiconductor device assembly, comprising:
a package substrate having an inner surface;
one or more semiconductor dies carried by the inner surface, wherein each of the one or more semiconductor dies is electrically coupled to the inner surface by one or more bond wires; and
a stacked capacitor device carried by the inner surface, wherein the stacked capacitor device comprises:
a first capacitor having a lower surface attached to the inner surface of the package substrate and an upper surface opposite the lower surface;
an interposer having a first side attached to the upper surface of the first capacitor, a second side opposite the first side, and a conductive via; and
a second capacitor attached to the second side of the interposer, wherein a first terminal of the first capacitor is electrically coupled to the inner surface of the package substrate, and wherein a second terminal of the second capacitor is electrically coupled to the first terminal through the conductive via.
2 . The semiconductor device assembly of claim 1 wherein the first terminal and the second terminal are ground terminals.
3 . The semiconductor device assembly of claim 1 , further comprising a bond wire electrically coupling a terminal of the second capacitor to the inner surface of the package substrate.
4 . The semiconductor device assembly of claim 1 wherein the interposer includes a porch region overhanging the package substrate and a bonding region on the second side in the porch region, wherein the first terminal of the second capacitor is electrically coupled to the bonding region, and wherein the semiconductor device assembly further comprises a bond wire electrically coupling the bonding region to the inner surface.
5 . The semiconductor device assembly of claim 1 wherein the one or more semiconductor dies includes a controller die, and wherein the semiconductor device assembly further comprises a bond wire electrically coupling at least one terminal of the second capacitor directly to the controller die.
6 . The semiconductor device assembly of claim 5 , further comprising a second bond wire electrically coupling a second terminal of the second capacitor directly to the controller die.
7 . The semiconductor device assembly of claim 1 wherein corresponding terminals in the first and second capacitors are vertically aligned.
8 . A semiconductor device assembly, comprising:
a package substrate having an upper surface that includes a stacking region and a peripheral region; and
a multi-capacitor component carried by the peripheral region, wherein the multi-capacitor component comprises:
a first capacitor having a lower surface attached to the upper surface of the package substrate and a top surface opposite the lower surface, wherein the first capacitor is electrically coupled to a first bond pad on the upper surface of the package substrate via a solder connection;
an interposer having a first side attached to the top surface of the first capacitor and a second side opposite the first side; and
a second capacitor attached to the second side of the interposer, wherein the second capacitor is electrically coupled to a second bond pad on the upper surface of the package substrate via a bond wire.
9 . The semiconductor device assembly of claim 8 wherein the bond wire is directly coupled to a terminal of the second capacitor.
10 . The semiconductor device assembly of claim 8 wherein the second capacitor is electrically coupled to a bond finger on the first side of the interposer, and wherein the bond wire is coupled between the bond finger and the second bond pad.
11 . The semiconductor device assembly of claim 8 wherein the first capacitor has a first footprint, and wherein the second capacitor has a second footprint generally equal to the first footprint.
12 . The semiconductor device assembly of claim 8 wherein the first capacitor is vertically aligned with the second capacitor.
13 . The semiconductor device assembly of claim 8 , further comprising a die stack that includes a controller die at a top of the die stack, and wherein the second capacitor is electrically coupled to the controller die via two or more bond wires.
14 . A method for manufacturing a stacked semiconductor device, the method comprising:
forming a stacked capacitor component, wherein forming the stacked capacitor component comprises:
providing an interposer comprising a first surface, a second surface opposite the first surface, first bond regions on the first surface, and second bond regions on the second surface opposite the first bond regions, wherein the interposer further comprises a conductive via extending between a corresponding pair of one of the first bond regions and one of the second bond regions;
attaching a first capacitor to the first bond regions; and
attaching a second capacitor to the second bond regions such that at least a portion of the second capacitor is vertically aligned with the first capacitor, wherein attaching the second capacitor includes electrically coupling a first terminal of the second capacitor the corresponding pair;
mounting the stacked capacitor component to a peripheral region of a package substrate;
mounting one or more semiconductor dies to a central region of the package substrate; and
electrically coupling a second terminal of the second capacitor in the stacked capacitor component to the package substrate through one or more bond wires.
15 . The method of claim 14 wherein mounting the stacked capacitor component to the peripheral region of the package substrate includes forming a solder joint between the first capacitor and the package substrate, and wherein the solder joint electrically couples the first capacitor to the package substrate.
16 . The method of claim 14 wherein attaching the first capacitor includes electrically coupling a first terminal of the first capacitor the corresponding pair such that the first terminal of the second capacitor is electrically coupled to the first terminal of the first capacitor through the conductive via.
17 . The method of claim 14 wherein the second terminal includes one or more bond pads at an upper surface of the second capacitor and wherein electrically coupling the second capacitor in the stacked capacitor component to the package substrate includes forming the one or more bond wires between the package substrate and the one or more bond pads at the surface of the second capacitor.
18 . The method of claim 14 wherein the interposer further includes a porch with a redistribution structure electrically coupled to one of the second bond regions, and wherein electrically coupling the second terminal of the second capacitor in the stacked capacitor component to the package substrate includes forming the one or more bond wires between the package substrate and the redistribution structure on the porch.