Power throttling mechanism using instruction rate limiting in high power machine-learning ASICs
A system contains a machine learning application specific integrated circuit (ASIC) and a power supply unit. The power supply unit and the ASIC are configured to be in data communication through dedicated pins on the ASIC and the power supply unit. The power supply unit detects a present power consumption of the ASIC. Upon determining that a threshold condition has been met, the power supply unit, responsive to the condition sends a digital signal to the ASIC. The ASIC contains a synchronizer which synchronizes the digital signal to be consistent with the ASICs internal clock frequency. A chip manager the synchronized signal and other signals to generate a throttling mask. The throttling mask is sent to a sequencer of the ASIC, which then limits the instruction flow into the processing units of the ASIC based on the mask. This in turn limits the power being consumed by the ASIC.
1 . A method of regulating power usage of an integrated circuit (IC) comprising:
receiving, by a synchronizer of the IC, a signal indicating an over current condition in the IC;
synchronizing, by the synchronizer, the signal to an internal clock domain of the IC to produce a synchronized signal in phase with the internal clock of the IC;
providing, by the synchronizer, the synchronized signal to a sequencer of the IC, the sequencer controlling a flow of instructions to be processed by the IC;
receiving, by the sequencer, the synchronized signal; and
reducing, by the sequencer in response to the received synchronized signal, the flow of instructions to limit a processing rate of the IC according to a throttling mask, the throttling mask limiting a rate of data to be processed by the IC.
2 . The method of claim 1 , wherein the signal indicating the over current condition is received by the synchronizer via a dedicated communication line.
3 . The method of claim 1 , further comprising generating, by a chip manager of the IC, the throttling mask based on the signal indicating the over current condition.
4 . The method of claim 1 , further comprising measuring, by a voltage regulator, a current load of the IC.
5 . The method of claim 4 , further comprising:
determining, by the voltage regulator, the current load meets a threshold level indicating the over current condition; and
providing, by the voltage regulator, the signal indicating the over current condition to the synchronizer.
6 . The method of claim 4 , further comprising:
determining, by the voltage regulator, the current load no longer meets a threshold level indicating the over current condition; and
providing, by the voltage regulator, a second signal indicating no over current condition to the sequencer.
7 . The method of claim 6 , further comprising restoring, by the sequencer, the flow of instructions to no longer limit a processing rate of the IC.
8 . An integrated circuit (IC) comprising:
a synchronizer configured to:
receive a signal from a voltage regulator indicating an over current condition in the IC; and
synchronize the signal to an internal clock domain to produce a synchronized signal in phase with the internal clock; and
a sequencer for controlling a flow of instructions to be processed by the IC, the sequencer configured to:
receive the synchronized signal; and
in response to the synchronized signal, reduce the flow of instructions to limit a processing rate of the IC according to a throttling mask, the throttling mask limiting a rate of data to be processed by the IC.
9 . The IC of claim 8 , wherein the signal indicating the over current condition is received by the synchronizer via a dedicated communication line.
10 . The IC of claim 8 , further comprising a chip manager configured to generate the throttling mask based on the signal indicating the over current condition.
11 . The IC of claim 8 , further comprising the voltage regulator, the voltage regulator configured to measure a current load of the IC.
12 . The IC of claim 11 , wherein the voltage regulator is further configured to:
determine the current load no longer meets a threshold level indicating the over current condition; and
provide a second signal indicating no over current condition to the sequencer.
13 . The IC of claim 12 , wherein the sequencer is further configured to restore the flow of instructions to no longer limit a processing rate of the IC.
14 . The IC of claim 11 , wherein the voltage regulator is further configured to:
determine the current load meets a threshold level indicating the over current condition; and
provide the signal indicating the over current condition to the synchronizer.
15 . A system comprising a voltage regulator and an integrated circuit (IC) coupled to the voltage regulator, wherein:
the voltage regulator is configured to:
measure a current load of the IC;
determine the current load meets a threshold level indicating an over current condition in the IC; and
provide a signal indicating the over current condition in the IC to the IC; and
the IC is configured to:
receive, by a synchronizer of the IC, the signal indicating the over current condition in the IC;
synchronize, by the synchronizer, the signal to an internal clock domain to produce a synchronized signal in phase with the internal clock;
provide, by the synchronizer, the synchronized signal to a sequencer of the IC, the sequencer controlling a flow of instructions to be processed by the IC; and
reduce, by the sequencer in response to the synchronized signal, the flow of instructions to limit a processing rate of the IC according to a throttling mask, the throttling mask limiting a rate of data to be processed by the IC.
16 . The system of claim 15 , wherein the IC is further configured to generate, by a chip manager, the throttling mask based on the signal indicating the over current condition.
17 . The system of claim 15 , wherein:
the voltage regulator is further configured to:
determine the current load no longer meets the threshold level indicating the over current condition; and
provide a second signal indicating no over current condition to the sequencer; and
the IC is further configured to restore, by the sequencer, the flow of instructions to no longer limit a processing rate of the IC.