Granted Patent B2

US 12,536,111 · App. 18/474,384 · Granted Jan 27, 2026

Inventors: Anwar Ali (San Jose, CA); Deepam Trivedi (Santa Clara, CA); Ho-Hsin Yeh (Belmont, CA)

Assignee: Avago Technologies International Sales Pte. Limited

G06F13/1673G06F13/1678G06F13/4234

Abstract

Claims (36)

1 . An apparatus comprising:

a circuit comprising a first connector and a second connector, the circuit being configured to send a first signal using the first connector to indicate a first selection, the second connector being positioned at a first location;

an interposer comprising a first interconnect and a second interconnect; and

a first memory device comprising a first selector and a third connector and a fourth connector, the first selector being coupled to the first connector through the first interconnect, the first selector being configured to couple the third connector to the second connector through the second interconnect based on the first signal, the third connector being positioned closer to the first location than the fourth connector;

wherein the first selection comprises a selection of a connector of the first memory device to be coupled to the second connector and is determined based on a spatial proximity associated with the first memory device; and

wherein the third connector is coupled to the second connector in accordance with a predetermined routing rule characterized by a first routing angle.

2 . The apparatus of claim 1 , further comprising a second memory device, wherein:

the circuit further comprises a fifth connector and a sixth connector, the circuit being configured to send a second signal using the fifth connector to indicate a second selection, the sixth connector being positioned at a second location;

the interposer further comprises a third interconnect and a fourth interconnect; and

the second memory device comprises a second selector and a seventh connector and an eighth connector, the second selector being coupled to the fifth connector through the third interconnect, the second selector being configured to couple the sixth connector to the seventh connector through the fourth interconnect based on the second signal, the seventh connector being closer to the second location than the eighth connector.

3 . The apparatus of claim 1 , wherein the circuit comprises an application specific integrated circuit.

4 . The apparatus of claim 1 , wherein the first memory device comprises a high bandwidth memory.

5 . The apparatus of claim 1 , wherein the first connector comprises a physical layer circuit.

6 . An apparatus comprising:

a circuit comprising a first connector and a second connector, the circuit being configured to send a first signal using the first connector to indicate a first selection, the second connector being positioned at a first location;

an interposer comprising a first interconnect and a second interconnect; and

a first buffer die comprising a first selector and a third connector and a fourth connector, the first selector being coupled to the first connector through the first interconnect, the first selector being configured to couple the third connector to the second connector through the second interconnect based on the first signal, the third connector being positioned closer to the first location than the fourth connector;

wherein the first selection comprises a selection of a connector of the first memory device to be coupled to the second connector and is determined based on a spatial proximity associated with the first memory device; and

wherein the third connector is coupled to the second connector in accordance with a predetermined routing rule characterized by a first routing angle.

7 . The apparatus of claim 6 , further comprising a first memory device coupled to the first buffer die.

8 . The apparatus of claim 6 , further comprising a first memory device coupled to the interposer.

9 . The apparatus of claim 8 , wherein the first memory device comprises a high bandwidth memory.

10 . The apparatus of claim 6 , wherein the circuit comprises an application specific integrated circuit.

11 . The apparatus of claim 6 , wherein the first buffer die is coupled to the interposer.

12 . The apparatus of claim 6 , wherein the third connector is coupled to the second connector through the second interconnect.

13 . The apparatus of claim 6 , wherein the first selector comprises a multiplexor.

14 . The apparatus of claim 6 , wherein the first connector comprises a physical layer circuit.

15 . An apparatus comprising:

a circuit comprising a first connector and a second connector, the circuit being configured to send a first signal using the first connector to indicate a first selection, the second connector being positioned at a first location;

an interposer coupled to the circuit, the interposer comprising a first interconnect; and

a first memory device comprising a first selector and a third connector and a fourth connector, the first selector being coupled to the first connector through the first interconnect, the first selector being configured to couple the third connector to the second connector based on the first signal, the third connector being positioned closer to the first location than the fourth connector;

wherein the first selection comprises a selection of a connector of the first memory device to be coupled to the second connector and is determined based on a spatial proximity associated with the first memory device; and

wherein the third connector is coupled to the second connector in accordance with a predetermined routing rule characterized by a first routing angle.

16 . The apparatus of claim 15 , wherein the circuit comprises an application-specific integrated circuit.

17 . The apparatus of claim 15 , wherein the first memory device comprises a high bandwidth memory.

18 . The apparatus of claim 15 , wherein the first selector comprises a multiplexor.

Assignments (1)

Continuity (2)

References Cited (22)