IP Library › Granted Patent US 12,536,964
Granted Patent B2
US 12,536,964 · App. 18/921,796 · Granted Jan 27, 2026

Display device

Inventors: Kihyun Pyun (Yongin-si, KR); Seung-Woon Shin (Yongin-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
G09G3/3266G09G3/3233G09G2300/0819G09G2300/0852G09G2310/0286G09G2310/08G09G2320/0233G09G2330/021
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,536,964
App. No.
18/921,796
Granted
Jan 27, 2026
Kind
B2
Abstract

A display device includes a display panel. The display panel includes a plurality of pixels receiving a first scan signal and a second scan signal, and a scan driver. The scan driver includes a first stage and a second stage arranged sequentially. A first pulse width of the second scan signal output from the first stage is different from a second pulse width of the second scan signal output from the second stage, when the second scan signal output from each of the first stage and the second stage is activated simultaneously.

Claims (67)

1 . An electronic A display device, comprising:

a display device comprising a display panel in which an active area and a peripheral area disposed adjacent to the active area are defined,

wherein the display panel includes:

a plurality of pixels disposed in the active area and configured to receive a first scan signal and a second scan signal; and

a scan driver disposed in the peripheral area and connected to the plurality of pixels,

wherein the scan driver includes a plurality of stages arranged sequentially,

wherein the plurality of stages includes a first stage and a second stage, and

wherein a first pulse width of the second scan signal output from the first stage is different from a second pulse width of the second scan signal output from the second stage, when the second scan signal output from each of the first stage and the second stage is activated simultaneously,

wherein the display panel operates during a plurality of frames,

wherein each of the plurality of frames operates in a first mode or a second mode different from the first mode,

wherein each of the plurality of stages outputs an activated first scan signal and the activated second scan signal, when operating only in the first mode,

wherein each of the plurality of stages outputs the activated second scan signal, when operating only in the second mode, and

wherein each of the first stage and the second stage outputs the second scan signal activated at a same time, when simultaneously operating in the first mode and the second mode.

2 . The electronic device of claim 1 , wherein the second pulse width is narrower than the first pulse width when the second stage is disposed after the first stage.

3 . The electronic device of claim 1 , wherein each of the first stage and the second stage includes:

a first scan output circuit including a first output node configured to output the first scan signal;

a second scan output circuit including a second output node configured to output the second scan signal;

a controller circuit including a plurality of control transistors electrically connected to a control node; and

a compensation circuit connected to the second scan output circuit.

4 . A display device, comprising:

a display panel in which an active area and a peripheral area disposed adjacent to the active area are defined,

wherein the display panel includes:

a plurality of pixels disposed in the active area and configured to receive a first scan signal and a second scan signal; and

a scan driver disposed in the peripheral area and connected to the plurality of pixels,

wherein the scan driver includes a plurality of stages arranged sequentially,

wherein the plurality of stages includes a first stage and a second stage, and

wherein a first pulse width of the second scan signal output from the first stage is different from a second pulse width of the second scan signal output from the second stage, when the second scan signal output from each of the first stage and the second stage is activated simultaneously,

wherein each of the first stage and the second stage includes:

a first scan output circuit including a first output node configured to output the first scan signal;

a second scan output circuit including a second output node configured to output the second scan signal;

a controller circuit including a plurality of control transistors electrically connected to a control node; and

a compensation circuit connected to the second scan output circuit,

wherein the compensation circuit includes:

an inverter circuit connected to the first output node; and

a multiplexer circuit connected to the first output node and the inverter circuit.

5 . The display device of claim 4 , wherein the multiplexer circuit receives a first clock signal having the second pulse width.

6 . The display device of claim 5 , wherein the second stage generates and outputs the second scan signal based on the first clock signal.

7 . The display device of claim 4 , wherein the compensation circuit further includes a control circuit connected to the control node and configured to control a voltage level of the control node.

8 . The display device of claim 7 , wherein the control node is in an active state when the second scan signal is output.

9 . The display device of claim 4 , wherein the first stage generates and outputs the second scan signal based on the first scan signal.

10 . The display device of claim 4 , wherein, when the second scan signal output simultaneously from each of the first stage and the second stage is activated, in the first stage, the first scan signal has an active level, a signal output from the inverter circuit has an inactive level, and a signal output from the multiplexer circuit has an active level.

11 . The display device of claim 4 , wherein, when the second scan signal output simultaneously from each of the first stage and the second stage is activated, in the second stage, the first scan signal has an inactive level, a signal output from the inverter circuit has an active level, and a signal output from the multiplexer circuit has an active level of the second pulse width.

12 . A display device, comprising:

a display panel in which an active area and a peripheral area disposed adjacent to the active area are defined,

wherein the display panel includes:

a plurality of pixels disposed in the active area and configured to receive a first scan signal and a second scan signal; and

a scan driver disposed in the peripheral area and connected to the plurality of pixels,

wherein the scan driver includes a plurality of stages arranged sequentially,

wherein each of the plurality of stages includes:

a first scan output circuit electrically connected to a control node and including a first output node configured to output the first scan signal;

a second scan output circuit electrically connected to the control node and including a second output node configured to output the second scan signal; and

a compensation circuit connected to the second scan output circuit,

wherein the compensation circuit receives the first scan signal, a first clock signal having a first pulse width, and a second clock signal having a second pulse width different from the first pulse width,

wherein the compensation circuit outputs a signal corresponding to the first clock signal or the second clock signal depending on the first scan signal, and

wherein the second scan output circuit outputs the second scan signal based on the signal.

13 . The display device of claim 12 , wherein, when the second scan signal output from each of at least two stages among the plurality of stages is activated simultaneously, a first pulse width of the second scan signal output from one stage among the at least two stages is different from a second pulse width of the second scan signal output from another stage among the at least two stages.

14 . The display device of claim 13 , wherein, when the another stage is disposed after the one stage, the second pulse width of the second scan signal is narrower than the first pulse width of the second scan signal.

15 . The display device of claim 12 , wherein the compensation circuit includes:

an inverter circuit connected to the first output node;

a multiplexer circuit connected to the first output node and the inverter circuit; and

a control circuit connected to the control node and configured to control a state of the control node.

16 . The display device of claim 15 , wherein the display panel operates during a plurality of frames, and

wherein each of the plurality of frames operates in at least one of a first mode and a second mode different from the first mode.

17 . The display device of claim 16 , wherein the plurality of stages sequentially output the first scan signal and the second scan signal when operating in the first mode, and

wherein the plurality of stages sequentially output the second scan signal when operating in the second mode.

18 . The display device of claim 16 , wherein the one stage generates and outputs the second scan signal based on the first scan signal when the first mode and the second mode operate simultaneously.

19 . The display device of claim 16 , wherein the another stage generates and outputs the second scan signal based on the first clock signal when the first mode and the second mode operate simultaneously.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2025
From: PYUN, KIHYUN; SHIN, SEUNG-WOON
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 069823/0757 →
Priority Claims (1)
KR 10-2024-0009323 · Jan 22, 2024 · national
Continuity (1)
Related Publication 20250239228A1 · Jul 24, 2025
References Cited (12)
US 11605353B2 · Sang et al. · 2023 [cited by applicant]
US 11626070B2 · Yun et al. · 2023 [cited by applicant]
US 11817055B2 · Sang et al. · 2023 [cited by applicant]
US 11823619B2 · Chung et al. · 2023 [cited by applicant]
US 20220028323A1 · In · 2022 [cited by examiner]
US 20220375412A1 · Kim · 2022 [cited by examiner]
CN 109243371A · 2019 [cited by examiner]
KR 1020180078928A · 2018 [cited by applicant]
KR 1020220022335A · 2022 [cited by applicant]
KR 1020220022406A · 2022 [cited by applicant]
KR 1020220041509A · 2022 [cited by applicant]
KR 1020220088602A · 2022 [cited by applicant]