Memory cell array including partitioned dual line structure and design method thereof
An integrated circuit includes is provided. The integrated circuit includes: a plurality of bit lines spaced apart from each other along a first direction and extending in a second direction perpendicular to the first direction through a first sub-array and a second sub-array neighboring the first sub-array in the second direction. Each of the plurality of bit lines includes: a first metal wiring extending in the second direction, the first metal wiring including a first portion and a second portion that is separated from the first portion by a first cutting portion; a third metal wiring extending in the second direction, and at least partially overlapping the first metal wiring along a third direction perpendicular to the first direction and the second direction; and two bridges electrically connecting the first metal wiring to the third metal wiring.
1 . An integrated circuit comprising:
a plurality of bit lines spaced apart from each other along a first direction and extending in a second direction perpendicular to the first direction through a first sub-array and a second sub-array neighboring the first sub-array in the second direction,
wherein each of the plurality of bit lines comprises:
a first metal wiring extending in the second direction, the first metal wiring comprising a first portion and a second portion that is separated from the first portion by a first cutting portion;
a third metal wiring extending in the second direction, and at least partially overlapping the first metal wiring along a third direction perpendicular to the first direction and the second direction; and
two bridges electrically connecting the first metal wiring to the third metal wiring.
2 . The integrated circuit of claim 1 , wherein the two bridges comprise:
a first bridge disposed in the first sub-array between the second sub-array and the first cutting portion; and
a second bridge disposed in the second sub-array.
3 . The integrated circuit of claim 1 , wherein each of the two bridges comprises:
a first via formed on the first metal wiring;
a second metal wiring formed on the first via, and having a length in the first direction greater than the first via; and
a second via formed on the second metal wiring.
4 . The integrated circuit of claim 1 , wherein the first sub-array comprises a plurality of bit cells,
wherein a first bridge of the two bridges is provided in the first sub-array, and
wherein the first cutting portion and the first bridge are spaced apart from the plurality of bit cells.
5 . The integrated circuit of claim 1 , wherein the second sub-array comprises a plurality of bit cells,
wherein a second bridge of the two bridges is provided in the second sub-array, and
wherein the second bridge is provided on a boundary of the plurality of bit cells.
6 . The integrated circuit of claim 1 , wherein the second sub-array further comprises a plurality of bridges spaced apart from each other along the second direction and electrically connecting the first metal wiring and the third metal wiring.
7 . The integrated circuit of claim 6 , wherein the second sub-array further comprises a second cutting portion repeatedly cutting the first metal wiring constituting the plurality of bit lines, at regular intervals in the second direction.
8 . The integrated circuit of claim 1 , further comprising a plurality of power lines,
wherein each of the plurality of power lines is disposed between a corresponding pair of the plurality of bit lines, and comprises:
a first metal wiring extending in the second direction, the first metal wiring comprising a first portion and a second portion that is separated from the first portion by a second cutting portion;
a third metal wiring extending in the second direction, and at least partially overlapping the first metal wiring along a third direction perpendicular to the first direction and the second direction; and
two bridges electrically connecting the first metal wiring to the third metal wiring.
9 . The integrated circuit of claim 8 , wherein the second sub-array comprises a plurality of bit cells,
wherein the two bridges formed in each of the plurality of power lines, a bridge disposed in the second sub-array is disposed in a boundary of the plurality of bit cells, and a bridge other than the bridge disposed in the boundary of the plurality of bit cells is spaced apart from the plurality of bit cells.
10 . The integrated circuit of claim 8 , wherein the second sub-array comprises a plurality of bit cells, and
bridges disposed in the second sub-array of the two bridges disposed in each of the plurality of power lines are all spaced apart from the plurality of bit cells.
11 . The integrated circuit of claim 8 , wherein the second sub-array comprises a plurality of bit cells, and
bridges disposed in the second sub-array of the two bridges disposed in each of the plurality of power lines are provided along a boundary of the plurality of bit cells.
12 . The integrated circuit of claim 8 , wherein the second sub-array further comprises a plurality of bridges spaced apart from each other along the second direction and electrically connecting the first metal wiring and the third metal wiring, and the plurality of power lines.
13 . The integrated circuit of claim 12 , wherein the second sub-array further comprises a second cutting portion repeatedly cutting the first metal wiring constituting the plurality of bit lines, and the plurality of power lines, in the second direction at regular intervals.
14 . The integrated circuit of claim 8 , wherein the second sub-array further comprises a second cutting portion cutting the third metal wiring such that the third metal wiring constituting the plurality of power lines is included only in the first sub-array.
15 . An integrated circuit comprising:
a first sub-array comprising a first structure that comprises a static random access memory (SRAM) cell and a second structure;
a second sub-array neighboring the first sub-array in a second direction;
a multiplexer portion configured to transmit signals to the first sub-array and the second sub-array according to a column address and a sub-array address;
a plurality of first metal wirings spaced apart from each other along a first direction, and extending through the first structure and the second structure in a second direction perpendicular to the first direction, each of the plurality of first metal wirings comprising a first portion and a second portion that is separated from the first portion by a first cutting portion;
a third metal wiring formed above the plurality of first metal wirings and extending in the second direction through the first structure and the second structure, and at least partially overlapping the plurality of first metal wirings along a third direction perpendicular to the first direction and the second direction;
a first bridge formed in the second structure between the plurality of first metal wirings and the third metal wiring, and electrically connecting a first metal wiring among the plurality of first metal wirings to the third metal wiring; and
a second bridge electrically connecting the first metal wiring to the third metal wiring.
16 . The integrated circuit of claim 15 , wherein the second sub-array comprises the first structure and a third structure comprising an SRAM cell,
wherein the plurality of first metal wirings extend in the second direction through the third structure;
wherein the third metal wiring extends in the second direction through the third structure, and
wherein the second bridge is provided in the third structure at a boundary of SRAM cells, and is formed in a stack structure between the plurality of first metal wirings and the third metal wiring.
17 . The integrated circuit of claim 15 , wherein the second sub-array comprises a plurality of third structures repeatedly provided in the second direction,
wherein each of the plurality of third structures comprises an SRAM cell,
wherein the plurality of first metal wirings extend through each of the plurality of third structures,
wherein the third metal wiring extends through each of the plurality of third structures, and
wherein the second bridge is provided in the plurality of third structures at a boundary of SRAM cells, and is formed in a stack structure between the plurality of first metal wirings and the third metal wiring.
18 . The integrated circuit of claim 15 , wherein the second sub-array comprises a plurality of fourth structures repeatedly provided in the second direction,
wherein each of the plurality of fourth structures comprises an SRAM cell,
wherein each of the plurality of first metal wirings comprises a plurality of portions respectively provided in the plurality of fourth structures and separated from each other by a plurality of second cutting portions,
wherein the third metal wiring extends through each of the plurality of fourth structures, and
wherein the second bridge is provided in the each of the plurality of fourth structures at a boundary of SRAM cells, and is formed in a stack structure between the plurality of first metal wirings and the third metal wiring.
19 . The integrated circuit of claim 15 , wherein the first bridge comprises:
a first via formed on the plurality of first metal wirings;
a second metal wiring formed on the first via, and farther in the first direction than the first via; and
a second via formed on the second metal wiring.
20 . An integrated circuit comprising:
a first metal wiring of a word line extending in a first direction through a first segment and a second segment of the integrated circuit, the first metal wiring comprising a first portion and a second portion that is separated from the first portion by a first cutting portion;
a second metal wiring of the word line extending in the first direction, and at least partially overlapping the first metal wiring along a second direction perpendicular to the first direction; and
two bridges formed in a stack structure between the first metal wiring and the second metal wiring, and electrically connecting the first metal wiring to the second metal wiring at both ends of the second segment.