Memory with programmable refresh order and stagger time
Memory devices and systems with programmable refresh order and stagger times are disclosed herein. In one embodiment, a memory device includes a first memory bank group and a second memory bank group. The memory device is configured, in response to a refresh command, to perform a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time after the first time. The memory device is further configured to perform, in response to a read or write command, a read or write operation on the first memory bank group, the second memory bank group, or both the first and second memory bank groups after beginning the first refresh operation and before completing the second refresh operation.
1 . A memory system, comprising:
one or more memory devices; and
one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
receive a command to refresh a plurality of regions of the memory system;
perform, during a duration, a refresh operation on a first region of the plurality of regions based at least in part on receiving the command;
identify that a second region of the plurality of regions is idle for the duration based at least in part on receiving the command; and
perform, during the duration, one or more access operations on the second region based at least in part on identifying the second region is idle during the duration.
2 . The memory system of claim 1 , wherein the one or more controllers are further configured to cause the memory system to:
perform, during a second duration, a second refresh operation on the second region based at least in part on receiving the command;
identify that the first region is idle for the second duration based at least in part on receiving the command; and
perform, during the second duration, one or more second access operations on the first region based at least in part on identifying the first region is idle during the second duration.
3 . The memory system of claim 1 , wherein the one or more controllers are further configured to cause the memory system to:
identify a plurality of time offsets between performing each refresh operation for the plurality of regions,
wherein that identifying the second region is idle is based at least in part on identifying a time offset from the plurality of time offsets between performing the refresh operation and performing a second refresh operation on the second region.
4 . The memory system of claim 3 , wherein identifying that the time offset is based at least in part on accessing the plurality of time offsets stored in one or more registers of the memory system.
5 . The memory system of claim 1 , wherein the one or more controllers are further configured to cause the memory system to:
identify an order for performing each refresh operation for the plurality of regions,
wherein identifying that the second region is idle is based at least in part on identifying that performing the refresh operation is prior to performing a second refresh operation on the second region in the order.
6 . The memory system of claim 5 , wherein identifying that performing the refresh operation is prior to performing the second refresh operation on the second region in the order is based at least in part on accessing the order stored in one or more registers of the memory system.
7 . The memory system of claim 5 , wherein identifying that performing the refresh operation is prior to performing the second refresh operation on the second region in the order is based at least in part on receiving an indication of the order.
8 . The memory system of claim 1 , wherein identifying that the second region is idle for the duration is based at least in part on one or more array timers associated with performing the refresh operation.
9 . The memory system of claim 1 , wherein the refresh operation is a row hammer refresh operation.
10 . The memory system of claim 1 , wherein each region of the plurality of regions comprises one or more memory banks.
11 . The memory system of claim 1 , wherein each region of the plurality of regions comprises one or more rows or columns of the memory system.
12 . A method by a memory system, comprising:
receiving a command to refresh a plurality of regions of the memory system;
performing, during a duration, a refresh operation on a first region of the plurality of regions based at least in part on receiving the command;
identifying that a second region of the plurality of regions is idle for the duration based at least in part on receiving the command; and
performing, during the duration, one or more access operations on the second region based at least in part on identifying the second region is idle during the duration.
13 . The method of claim 12 , further comprising:
performing, during a second duration, a second refresh operation on the second region based at least in part on receiving the command;
identifying that the first region is idle for the second duration based at least in part on receiving the command; and
performing, during the second duration, one or more second access operations on the first region based at least in part on identifying the first region is idle during the second duration.
14 . The method of claim 12 , further comprising:
identifying a plurality of time offsets between performing each refresh operation for the plurality of regions,
wherein identifying that the second region is idle is based at least in part on identifying a time offset from the plurality of time offsets between performing the refresh operation and performing a second refresh operation on the second region.
15 . The method of claim 14 , wherein identifying the time offset is based at least in part on accessing the plurality of time offsets stored in one or more registers of the memory system.
16 . The method of claim 12 , further comprising:
identifying an order for performing each refresh operation for the plurality of regions,
wherein identifying that the second region is idle is based at least in part on identifying that performing the refresh operation is prior to performing a second refresh operation on the second region in the order.
17 . The method of claim 16 , wherein identifying that performing the refresh operation is prior to performing the second refresh operation on the second region in the order is based at least in part on accessing the order stored in one or more registers of the memory system.
18 . The method of claim 16 , wherein identifying that performing the refresh operation is prior to performing the second refresh operation on the second region in the order is based at least in part on receiving an indication of the order.
19 . The method of claim 12 , wherein identifying the second region is idle for the duration is based at least in part on one or more array timers associated with performing the refresh operation.
20 . A non-transitory computer-readable medium comprising code comprising instructions which, when executed by one or more processors of an electronic device, cause the electronic device to:
receive a command to refresh a plurality of regions of a memory system;
perform, during a duration, a refresh operation on a first region of the plurality of regions based at least in part on receiving the command;
identify a second region of the plurality of regions is idle for the duration based at least in part on receiving the command; and
perform, during the duration, one or more access operations on the second region based at least in part on identifying the second region is idle during the duration.