RC-tuned wordline underdrive circuit
An apparatus and method for both reducing power consumption and increasing read access stability of a memory array. An integrated circuit includes a memory array with memory bit cells arranged as multiple rows and multiple columns. The array also includes multiple word line driver circuits configured to generate a corresponding word line for multiple rows. The array includes an underdrive circuit configured to adjust, via a configurable resistor-capacitor circuit, a rate of change of a voltage level of a word line. The configurable resistor-capacitor circuit controls the store data rate of the charging of the selected word line and allows the selected word line to charge to the power supply voltage. The configurable resistor-capacitor circuit controls the rate of charging without creating a direct current path between the power supply voltage and the ground reference level that would increase power consumption.
1 . An integrated circuit comprising:
an array of memory bit cells arranged as a plurality of rows and a plurality of columns, each configured to store data;
a plurality of word line driver circuits, each configured to generate a corresponding word line for the plurality of rows of the array of memory bit cells; and
an underdrive circuit configured to adjust, via a configurable resistor-capacitor circuit, a rate of change in a voltage level of a given word line generated by a word line driver circuit of the plurality of word line driver circuits.
2 . The integrated circuit as recited in claim 1 , wherein one or more of the plurality of word line driver circuits comprises a p-type transistor comprising:
a source terminal connected to a corresponding word line;
a gate terminal configured to receive an analog bias input signal; and
a drain terminal connected to an end of a capacitor of the configurable resistor-capacitor circuit of the underdrive circuit.
3 . The integrated circuit as recited in claim 1 , wherein one or more of the plurality of word line driver circuits comprises a p-type transistor comprising:
a source terminal connected to a corresponding word line;
a gate terminal configured to receive an inverted value of the corresponding word line; and
a drain terminal connected to the configurable resistor-capacitor circuit of the underdrive circuit.
4 . The integrated circuit as recited in claim 3 , wherein the underdrive circuit is further configured to disconnect a capacitor of the configurable resistor-capacitor circuit during accesses of the array of memory bit cells.
5 . The integrated circuit as recited in claim 1 , wherein the underdrive circuit is further configured to discharge a capacitor of the configurable resistor-capacitor circuit between accesses of the array of memory bit cells.
6 . The integrated circuit as recited in claim 5 , wherein the underdrive circuit is further configured to disable, via a word line clock signal during an access of the array of memory bit cells, an n-type pulldown transistor utilized to discharge the capacitor.
7 . The integrated circuit as recited in claim 1 , wherein an end of a capacitor of the configurable resistor-capacitor circuit is connected to a metal route, wherein a portion of the metal route that traverses the array of memory bit cells has a length that is less than a length of the given word line that traverses the array of memory bit cells.
8 . A method comprising:
storing data in an array of memory bit cells arranged as a plurality of rows and a plurality of columns, each configured to store data;
generating, by each of a plurality of word line driver circuits, a corresponding word line for the plurality of rows of the array of memory bit cells; and
adjusting, via a configurable resistor-capacitor circuit of an underdrive circuit coupled to the plurality of word line driver circuits, a rate of change in a voltage level of a given word line generated by a given word line driver circuit of the plurality of word line driver circuits.
9 . The method as recited in claim 8 , further comprising:
generating a corresponding word line of the given word line driver circuit by a source terminal of a p-type transistor of the given word line driver circuit;
receiving an analog bias input signal by a gate terminal of the p-type transistor; and
charging a configurable capacitor by a drain terminal of the p-type transistor.
10 . The method as recited in claim 8 , further comprising:
generating a corresponding word line of the given word line driver circuit by a source terminal of a p-type transistor of the given word line driver circuit;
receiving an inverted value of the corresponding word line by a gate terminal of the p-type transistor; and
charging a configurable capacitor of the configurable resistor-capacitor circuit via a drain terminal of the p-type transistor and a configurable resistor of the configurable resistor-capacitor circuit.
11 . The method as recited in claim 10 , further comprising disconnecting, by the underdrive circuit, a capacitor of the configurable resistor-capacitor circuit during accesses of the array of memory bit cells.
12 . The method as recited in claim 8 , further comprising discharging, by the underdrive circuit, a capacitor of the configurable resistor-capacitor circuit between accesses of the array of memory bit cells.
13 . The method as recited in claim 12 , further comprising disabling, via a word line clock signal during an access of the array of memory bit cells, an n-type pulldown transistor utilized to discharge the capacitor.
14 . The method as recited in claim 8 , wherein an end of a capacitor of the configurable resistor-capacitor circuit is connected to a metal route, wherein a portion of the metal route that traverses the array of memory bit cells has a length that is less than a length of the given word line that traverses the array of memory bit cells.
15 . A computing system comprising:
a memory comprising:
an array of memory bit cells arranged as a plurality of rows and a plurality of columns, each configured to store data; and
a plurality of word line driver circuits, each configured to generate a corresponding word line for the plurality of rows of the array of memory bit cells; and
an underdrive circuit coupled to the plurality of word line driver circuits configured to adjust, via a configurable resistor-capacitor circuit, a rate of change in a voltage level of a given word line generated by a given word line driver circuit of the plurality of word line driver circuits; and
a processor configured to generate memory access requests targeting data stored in the memory.
16 . The computing system as recited in claim 15 , wherein one or more of the plurality of word line driver circuits comprises a p-type transistor comprising:
a source terminal connected to a corresponding word line;
a gate terminal configured to receive an analog bias input signal; and
a drain terminal connected to an end of a capacitor of the configurable resistor-capacitor circuit of the underdrive circuit.
17 . The computing system as recited in claim 15 , wherein one or more of the plurality of word line driver circuits comprises a p-type transistor comprising:
a source terminal connected to a corresponding word line;
a gate terminal configured to receive an inverted value of the corresponding word line; and
a drain terminal connected to the configurable resistor-capacitor circuit of the underdrive circuit.
18 . The computing system as recited in claim 17 , wherein the underdrive circuit is further configured to disconnect a capacitor of the configurable resistor-capacitor circuit during accesses of the array of memory bit cells.
19 . The computing system as recited in claim 15 , wherein the underdrive circuit is further configured to discharge a capacitor of the configurable resistor-capacitor circuit between accesses of the array of memory bit cells.
20 . The computing system as recited in claim 19 , wherein the underdrive circuit is further configured to disable, via a word line clock signal during an access of the array of memory bit cells, an n-type pulldown transistor utilized to discharge the capacitor.