Memory device and sense amplifier control circuit for offset cancellation
A first inverter includes second and third transistors coupled at a third node. A second inverter includes fourth and fifth transistors coupled at a fourth node. A sixth transistor is between the fifth transistor's gate and the third node. A seventh transistor is between the third transistor's gate and the fourth node. An eighth transistor is between the third transistor's gate and the third node. A ninth transistor is between the fifth transistor's gate and the fourth node. A voltage of the eighth and ninth transistors' gates lowers at a first time. A state is formed with voltages applied to first and second nodes of the first and second inverters at a second time. A voltage of the sixth and seventh transistors' gates rises between the first and second times.
1 . A memory device comprising:
a capacitor;
a first transistor coupled to the capacitor at a first end;
a first inverter circuit coupled between a first node and a second node and including a p-type second transistor and an n-type third transistor that are coupled in series at a third node;
a second inverter circuit coupled between the first node and the second node and including a p-type fourth transistor and an n-type fifth transistor that are coupled in series at a fourth node;
a sixth transistor coupled between a gate of the fifth transistor and the third node;
a seventh transistor coupled between a gate of the third transistor and the fourth node and between a second end of the first transistor and the fourth node;
an eighth transistor coupled between the gate of the third transistor and the third node;
a ninth transistor coupled between the gate of the fifth transistor and the fourth node;
a first circuit that supplies a first signal that falls at a first time or a second signal obtained by delaying the first signal to a gate of the eighth transistor and a gate of the ninth transistor; and
a second circuit that supplies a third signal that rises based on falling of the first signal or a fourth signal obtained by delaying the third signal to a gate of the sixth transistor and a gate of the seventh transistor,
the second circuit includes a NAND gate that receives the first signal at a first input and outputs the third signal.
2 . The memory device according to claim 1 , wherein
the first circuit includes a pulse generation circuit that outputs the first signal of a first level from a second time to the first time.
3 . The memory device according to claim 2 , further comprising a delay circuit that, upon receiving a fifth signal, outputs a sixth signal obtained by delaying the fifth signal, wherein
the NAND gate receives the sixth signal at a second input, and
the pulse generation circuit outputs the first signal of the first level from the second time to the first time upon receiving the fifth signal before the second time.
4 . The memory device according to claim 3 , wherein
the first circuit includes a first number of inverter circuits that are coupled in series, receives the first signal, and outputs the second signal, the first number being an even number, and
the second circuit includes inverter circuits that are coupled in series, receives the third signal, and outputs the fourth signal, the inverter circuits being equal in number to the first number of inverter circuits.