Method for producing a buried interconnect rail of an integrated circuit chip
A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.
1 . A method for producing a buried interconnect rail of an integrated circuit chip, the method comprising:
providing a device wafer comprising a semiconductor layer on top, the semiconductor layer having a front surface and a back surface, and further comprising a dielectric layer on at least one or more parts of the front surface of the semiconductor layer;
producing a trench in the semiconductor layer or through the dielectric layer and into the semiconductor layer;
producing a dielectric liner on inner surfaces of the trench;
removing the dielectric liner from a bottom of the trench or from one or more parts of the bottom of the trench, the one or more parts of the bottom of the trench being determined by producing a mask having one or more openings corresponding to the one or more parts of the bottom of the trench, while maintaining the dielectric liner on sidewalls of the trench;
applying an etch process that is selective with respect to the dielectric liner or with respect to the dielectric liner and the mask, thereby creating at least one cavity extending downward and laterally outward from the bottom of the trench or from each of the one or more parts of the bottom of the trench;
filling the at least one cavity and the trench with an electrically conductive material to thereby form the buried interconnect rail, wherein the buried interconnect rail comprises a narrow portion inside the trench and at least one wider portion inside the at least one cavity, and filling the at least one cavity and the trench results in a void in a center of the at least one wider portion of the buried interconnect rail;
thinning the device wafer until the back surface of the semiconductor layer is exposed;
producing a via opening through the back surface, the via opening being wider than the narrow portion of the buried interconnect rail and fully overlapping the narrow portion so that the via opening also overlaps at least part of the wider portion of the buried interconnect rail,
after producing the via opening, removing a portion of the wider portion of the buried interconnect rail until an inner surface of a portion of the void is exposed; and
filling the portion of the void and the via opening with an electrically conductive material to form a through-silicon via (TSV) connection that contacts one of the at least one wider portion of the buried interconnect rail.
2 . The method according to claim 1 , wherein:
the etch process is an isotropic etch process, and
the at least one cavity has a spherical shape or a diamond shape, as seen in a cross section oriented perpendicularly with respect to a longitudinal direction of the trench.
3 . The method according to claim 1 , wherein:
the etch process is an atomic layer etch process, and
the at least one cavity has a rectangular shape, as seen in a cross section oriented perpendicularly with respect to a longitudinal direction of the trench.
4 . The method according to claim 1 , further comprising:
deepening the bottom of the trench or the one or more parts of the bottom of the trench while maintaining the dielectric liner on the sidewalls of the trench, thereby creating one or more extensions of the trench, wherein:
no liner is present on the sidewalls of the one or more extensions, and
the etch process for creating the at least one cavity is applied after creating the one or more extensions.
5 . The method according to claim 4 , wherein:
the etch process is an isotropic etch process, and
the at least one cavity has a spherical shape or a diamond shape, as seen in a cross section oriented perpendicularly with respect to a longitudinal direction of the trench.
6 . The method according to claim 4 , wherein:
the etch process is an atomic layer etch process, and
the at least one cavity has a rectangular shape, as seen in a cross section oriented perpendicularly with respect to a longitudinal direction of the trench.
7 . The method according to claim 1 , wherein:
the dielectric liner includes a first dielectric liner, and
a second dielectric liner is deposited on the first dielectric liner and on an inner surface of the at least one cavity, before filling the at least one cavity and the trench with the electrically conductive material.
8 . The method according to claim 1 , wherein the dielectric liner is removed from the sidewalls of the trench before filling the at least one cavity and the trench.
9 . The method according to claim 8 , wherein a second dielectric liner is deposited on the sidewalls of the trench and on an inner surface of the at least one cavity, before filling the at least one cavity and the trench with the electrically conductive material.
10 . The method according to claim 1 , wherein the buried interconnect rail is arranged as a buried power rail.
11 . The method according to claim 1 , wherein the electrically conductive material that fills the at least one cavity and the trench and the electrically conductive material that fills the portion of the void and the via opening are a metal.
12 . The method according to claim 1 , wherein filling the at least one cavity and the trench with an electrically conductive material is provided by atomic layer deposition.
13 . The method according to claim 1 , wherein filling the at least one cavity and the trench with an electrically conductive material is provided by plating, or by physical vapor deposition and reflow cycling.
14 . The method according to claim 1 , wherein the producing the mask occurs by forming a stack of spin-on-carbon and spin-on-glass.
15 . The method according to claim 1 , wherein the dielectric liner includes a layer of silicon oxide, silicon nitride, or silicon oxycarbide.
16 . The method according to claim 1 , wherein the integrated circuit chip comprises a complementary metal oxide semiconductor layout of fin field-effect transistors.
17 . The method according to claim 1 , wherein the at least one wider portion of the buried interconnect rail extends along an entire length of the buried interconnect rail.
18 . The method according to claim 1 , wherein the at least one wider portion of the buried interconnect rail are produced locally at one or more locations where the TSV connection is located.
19 . The method according to claim 1 , wherein the at least one cavity includes a plurality of cavities formed at various locations along the trench.
20 . The method according to claim 1 , wherein removing the dielectric liner occurs by a wet etch process or a dry isotropic etch process.