Low complexity crosstalk mitigation in a nonvolatile memory
A storage system includes circuitry and multiple memory cells. The memory cells are arranged in multiple Word Lines (WLs), including a target WL. The circuitry includes combinational logic implemented in hardware, the circuitry configured to: read a page from a group of target memory cells in the target WL multiple times to produce multiple respective target binary readouts, read a group of neighbor memory cells in a WL neighboring to the target WL so as to produce a single neighbor binary readout, apply the combinational logic to both the target binary readouts and the neighbor binary readout to produce (i) output bits of the page, and (ii) respective binary confidence levels associated with the output bits, and transmit the output bits and the binary confidence levels to a controller.
1 . A storage system, comprising:
multiple memory cells arranged in multiple Word Lines (WLs), including a target WL; and
circuitry comprising combinational logic implemented in hardware, the circuitry configured to:
read a page from a group of target memory cells in the target WL multiple times, so as to produce multiple respective target binary readouts including at least a left target binary readout, a middle target binary readout, and a right target binary readout;
read a group of neighbor memory cells in a WL neighboring to the target WL so as to produce a single neighbor binary readout;
apply the combinational logic to calculate (i) output bits of the page, and (ii) respective binary confidence levels associated with the output bits, as logical expressions of the left target binary readout, the middle target binary readout, the right target binary readout and the neighboring binary readout; and
transmit the output bits and the binary confidence levels to a controller.
2 . The storage system according to claim 1 , wherein the combinational logic is configured to set the output bits to respective bits of the middle binary readout, and to calculate the binary confidence levels by comparing between the left target binary readout and the middle target binary readout, or between the middle target binary readout and the right target binary readout depending on the neighbor binary readout.
3 . The storage system according to claim 1 , wherein the combinational logic is configured to calculate the output bits by selecting between the middle target binary readout and one of the left target binary readout and the right target binary readout based on the neighbor binary readout.
4 . The storage system according to claim 1 , wherein the combinational logic is configured to calculate the binary confidence levels by selecting, based on the neighbor binary readout, between (i) a first comparison outcome between the middle target binary readout and the left target binary readout, and (ii) a second comparison outcome between the middle target binary readout and the right target binary readout.
5 . The storage system according to claim 1 , wherein at least some of the memory cells in the group of target memory cells are subjected to voltage shifts due to respective neighbor memory cells having high or low voltages, and wherein the combinational logic is configured to determine the output bits and the binary confidence levels so as to compensate for the voltage shifts.
6 . The storage system according to claim 1 , wherein a voltage axis is divided by multiple specified read thresholds into high confidence zones and low confidence zones, and wherein the combinational logic is configured to determine the output bits in the high confidence zones independently of the neighbor memory cells.
7 . The storage system according to claim 1 , wherein the combinational logic is configured to set undetermined output bits for target memory cells evaluated as having low confidence levels.
8 . The storage system according to claim 1 , wherein the circuitry resides in a memory device comprising the memory cells.
9 . A method for data storage, comprising:
in a storage system comprising circuitry that comprises combinational logic implemented in hardware, and multiple memory cells arranged in multiple Word Lines (WLs), including a target WL,
reading by the circuitry a page from a group of target memory cells in the target WL multiple times, so as to produce multiple respective target binary readouts including at least a left target binary readout, a middle target binary readout, and a right target binary readout;
reading by the circuitry a group of neighbor memory cells in a WL neighboring to the target WL so as to produce a single neighbor binary readout;
applying the combinational logic to calculate (i) output bits of the page, and (ii) respective binary confidence levels associated with the output bits, as logical expressions of the left target binary readout, the middle target binary readout, the right target binary readout and the neighboring binary readout; and
transmitting the output bits and the binary confidence levels to a controller.
10 . The method according to claim 9 , wherein applying the combinational logic comprises setting the output bits to respective bits of the middle binary readout, and calculating the binary confidence levels by comparing between the left target binary readout and the middle target binary readout, or between the middle target binary readout and the right target binary readout depending on the neighbor binary readout.
11 . The method according to claim 9 , wherein applying the combinational logic comprises selecting between the middle target binary readout and one of the left target binary readout and the right target binary readout based on the neighbor binary readout.
12 . The method according to claim 9 , wherein applying the combinational logic comprises calculating the binary confidence levels by selecting, based on the neighbor binary readout, between (i) a first comparison outcome between the middle target binary readout and the left target binary readout, and (ii) a second comparison outcome between the middle target binary readout and the right target binary readout.
13 . The method according to claim 9 , wherein at least some of the memory cells in the group of target memory cells are subjected to voltage shifts due to respective neighbor memory cells having high or low voltages, and comprising determining the output bits and the binary confidence levels so as to compensate for the voltage shifts.
14 . The method according to claim 9 , wherein a voltage axis is divided by multiple specified read thresholds into high confidence zones and low confidence zones, and comprising determining the output bits in the high confidence zones independently of the neighbor memory cells.
15 . The method according to claim 9 , and comprising, setting by the combinational logic undetermined output bits for target memory cells evaluated as having low confidence levels.
16 . The method according to claim 9 , wherein the circuitry resides in a memory device comprising the memory cells.
17 . A storage system, comprising:
multiple memory cells arranged in multiple Word Lines (WLs), including a target WL; and
circuitry comprising combinational logic implemented in hardware, the circuitry configured to:
read a page from a group of target memory cells in the target WL multiple times to produce multiple respective target binary readouts;
read a group of neighbor memory cells in a WL neighboring to the target WL so as to produce a single neighbor binary readout;
apply the combinational logic to both the target binary readouts and the neighbor binary readout to produce (i) output bits of the page, and (ii) respective binary confidence levels associated with the output bits; and
transmit the output bits and the binary confidence levels to a controller,
wherein a voltage axis is divided by multiple specified read thresholds into high confidence zones and low confidence zones, and wherein the combinational logic is configured to determine the output bits in the high confidence zones independently of the neighbor memory cells.