Methods and apparatus to reduce read-modify-write cycles for non-aligned writes
Methods, apparatus, systems and articles of manufacture are disclosed to reduce read-modify-write cycles for non-aligned writes. An example apparatus includes a memory that includes a plurality of memory banks, an interface configured to be coupled to a central processing unit, the interface to obtain a write operation from the central processing unit, wherein the write operation is to write a subset of the plurality of memory banks, and bank processing logic coupled to the interface and to the memory, the bank processing logic to determine the subset of the plurality of memory banks to write based on the write operation, and determine whether to cause a read operation to be performed in response to the write operation based on whether a number of addresses in the subset of the plurality of memory banks to write satisfies a threshold.
1 . A system, comprising:
a cache memory comprising a first memory bank and a second memory bank;
an interface configured to receive a write operation indicating to write first data to the first memory bank and second data to the second memory bank; and
bank processing logic configured to:
determine whether a combination of the first data and the second data corresponds to a sum of a data width of the first memory bank and a data width of the second memory bank; and
based on determining that the combination of the first data and the second data is less than the sum of the data width of the first memory bank and the data width of the second memory bank,
cause write of the first data to the first memory bank without read of first existing data from the first memory bank;
cause read of second existing data from the second memory bank;
cause merge of the second data and the second existing data read from the second memory bank to generate second merged data; and
cause write of the second merged data to the second memory bank.
2 . The system of claim 1 , wherein:
the bank processing logic is configured to:
based on determining that the combination of the first data and the second data corresponds to the sum of the data width of the first memory bank and the data width of the second memory bank,
cause write of the first data to the first memory bank without read of the first existing data from the first memory bank; and
cause write of the second data to the second memory bank without read of the second existing data from the second memory bank.
3 . The system of claim 1 , wherein:
the interface is configured to receive another write operation indicating to write third data to the first memory bank; and
the bank processing logic is further configured to:
determine whether the third data corresponds to the data width of the first memory bank; and
based on determining that the third data corresponds to the data width of the first memory bank, cause write of the third data to the first memory bank without read of the first existing data from the first memory bank.
4 . The system of claim 3 , wherein the bank processing logic is further configured to:
based on determining that the third data is less than the data width of the first memory bank,
cause read of the first existing data from the first memory bank;
cause merge of the third data and the first existing data read from the first memory bank to generate first merged data; and
cause write of the first merged data to the first memory bank.
5 . The system of claim 1 , wherein the cache memory includes sixteen memory banks configured to be accessible independently from each other.
6 . The system of claim 1 , further comprising:
a first store queue coupled to the first memory bank; and
a second store queue coupled to the second memory bank.
7 . The system of claim 6 , wherein:
read of the first existing data from the first data to the first memory bank is performed based on the first store queue; and
read of the second existing data from the second memory bank is performed based on the second store queue.
8 . The system of claim 1 , wherein the cache memory is a victim cache.
9 . The system of claim 1 , wherein the cache memory is a level one (L1) cache memory.
10 . A system, comprising:
a cache memory comprising a first memory bank and a second memory bank;
a processor configured to generate a write operation indicating to write first data to the first memory bank and second data to the second memory bank; and
bank processing logic configured to:
determine whether a combination of the first data and the second data is same as a sum of a data width of the first memory bank and a data width of the second memory bank; and
based on determining that the combination of the first data and the second data is less than the sum of the data width of the first memory bank and the data width of the second memory bank,
cause write of the first data to the first memory bank without read of first existing data from the first memory bank;
cause read of second existing data from the second memory bank;
cause merge of the second data and the second existing data read from the second memory bank to generate second merged data; and
cause write of the second merged data to the second memory bank.
11 . The system of claim 10 , wherein:
the bank processing logic is configured to:
based on determining that the combination of the first data and the second data is same as the sum of the data width of the first memory bank and the data width of the second memory bank,
cause write of the first data to the first memory bank without read of the first existing data from the first memory bank; and
cause write of the second data to the second memory bank without read of the second existing data from the second memory bank.
12 . The system of claim 10 , wherein:
the processor is configured to generate another write operation indicating to write third data to the first memory bank; and
the bank processing logic is further configured to:
determine whether the third data is same as the data width of the first memory bank; and
based on determining that the third data is same as the data width of the first memory bank, cause write of the third data to the first memory bank without read of the first existing data from the first memory bank.
13 . The system of claim 12 , wherein the bank processing logic is further configured to:
based on determining that the third data is less than the data width of the first memory bank,
cause read of the first existing data from the first memory bank;
cause merge of the third data and the first existing data read from the first memory bank to generate first merged data; and
cause write of the first merged data to the first memory bank.
14 . The system of claim 10 , wherein the cache memory includes sixteen memory banks configured to be accessible independently from each other.
15 . The system of claim 10 , further comprising:
a first store queue coupled to the first memory bank; and
a second store queue coupled to the second memory bank.
16 . The system of claim 15 , wherein:
read of the first existing data from the first memory bank is performed based on the first store queue; and
read of the second existing data from the second memory bank is performed based on the second store queue.
17 . The system of claim 10 , wherein the cache memory is a victim cache.
18 . The system of claim 10 , wherein the cache memory is a level one (L1) cache memory.